Difference between revisions of "AXEL Lite SOM/AXEL Lite Evaluation Kit/Interfaces and Connectors/JTAG"

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<section begin="History" />
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!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
 
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
 
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New layout documentation
 
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add JTAG EVB connector
 
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<section end="History" />
 
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__FORCETOC__
 
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<section begin="Body" />
 
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==On board JTAG connector==
 
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JTAG signals are routed to a dedicated connector on the AXEL Lite PCB.
 
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The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
 
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[[File:Axellite-jtag-conn.png|500px|frameless|border]]
 
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=== J7 - SOM Connector's pinout ===
 
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J7 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:
 
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[[File:AXEL Lite-EVB-JTAG-connector.png|thumb|center| 500px|JTAG connector]]
 
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{| class="wikitable"
 
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|-
 
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!Pin#
 
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!Pin name
 
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!Function
 
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!ARM-20 JTAG
 
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!Notes
 
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|1 || DGND || -
 
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|4,6,8,10,12,14,16,18,20|| For example documented on [https://www2.lauterbach.com/pdf/app_arm_jtag.pdf#page=3 Lauterbach specification]
 
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|2 || JTAG_TCK || -
 
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|9|| -
 
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|3 || JTAG_TMS || -
 
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|7|| 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
 
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|4 || JTAG_TDO || -
 
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|13|| 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
 
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|-
 
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|5 || JTAG_TDI || -
 
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|5|| 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
 
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|6 || JTAG_nTRST || -
 
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|3 (*) || 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
 
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|7 || CPU_PORn || -
 
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|15 (*)|| -
 
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|8 || N.C. || -
 
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|9 || N.C. || -
 
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|10 || JTAG_VREF || -
 
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|1|| 3V3 (BOARD_PGOOD driven signal)
 
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|}
 
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(*) keep the possibility to be unconnected
 
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=== JD1 - EVB Connector's pinout ===
 
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JD1 is a 10x1x2.54mm pinhole header. The following table reports the connector's pinout:
 
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[[File:SBC-AXEL-JTAG.png|thumb|center| 500px|EVB JTAG connector]]
 
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{| class="wikitable"
 
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|-
 
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!Pin#
 
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!Pin name
 
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!Function
 
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!Notes
 
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|1 || DGND || -
 
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|
 
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|2 || JTAG_TCK || -
 
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| -
 
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|3 || JTAG_TMS || -
 
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| 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
 
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|-
 
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|4 || JTAG_TDO || -
 
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| 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
 
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|-
 
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|5 || JTAG_TDI || -
 
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| 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
 
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|-
 
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|6 || JTAG_nTRST || -
 
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| 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
 
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|-
 
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|7 || JTAG_nRST || -
 
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| -
 
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|8 || N.C. || -
 
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| -
 
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|9 || N.C. || -
 
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| -
 
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|10 || JTAG_VREF || -
 
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|}
 
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[[Category:AXEL Lite]]
 

Revision as of 15:13, 7 November 2020

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History
Issue Date Notes
2020/09/22 New documentation layout



On board JTAG connector[edit | edit source]

JTAG signals are routed to a dedicated connector on the AXEL Lite PCB.

The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).

Axellite-jtag-conn.png

J7 - SOM Connector's pinout[edit | edit source]

J7 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:

JTAG connector
Pin# Pin name Function ARM-20 JTAG Notes
1 DGND - 4,6,8,10,12,14,16,18,20 For example documented on Lauterbach specification
2 JTAG_TCK - 9 -
3 JTAG_TMS - 7 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
4 JTAG_TDO - 13 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
5 JTAG_TDI - 5 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
6 JTAG_nTRST - 3 (*) 10K pull-up to 3V3 (BOARD_PGOOD driven signal)
7 CPU_PORn - 15 (*) -
8 N.C. - -
9 N.C. - -
10 JTAG_VREF - 1 3V3 (BOARD_PGOOD driven signal)

(*) keep the possibility to be unconnected

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