Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Peripherals/PCI Express"

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__FORCETOC__
 
 
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<section begin=Body/>
  
 
==Peripheral PCI Express ==
 
==Peripheral PCI Express ==
PCI Express (Peripheral Component Interconnect Express''')''' is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards.
 
 
The two PCI Express interface on MITO 8M SOM:
 
* PCIe1 is avaiable on SODIMM connector pinout
 
* PCIe2 is avaiable on ONE PIECE expansion connector J5
 
  
 
=== Description  ===
 
=== Description  ===
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The PCI Express interfaces available on MITO 8M is based on iMX8M SoC.  
 
The PCI Express interfaces available on MITO 8M is based on iMX8M SoC.  
  
The PCI Express interfaces supports the following standards and features:
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The two PCIe PHY 1-lines each upports 6.0 Gbps data rate and complies to PCI Express base specification 2.1.
* two PCIe PHY ports (1-lines each)
 
* up to 6.0 Gbps data rate
 
* complies to PCI Express base specification 2.1.
 
* 8B/10B Encoding / Decoding
 
* Supports Spread Spectrum Clocking in Transmitter and Receiver
 
  
 
===Pin mapping===
 
===Pin mapping===

Revision as of 14:21, 1 October 2020

History
Version Issue Date Notes
1.0.0 Oct 2020 First release


Peripheral PCI Express[edit | edit source]

Description[edit | edit source]

The PCI Express interfaces available on MITO 8M is based on iMX8M SoC.

The two PCIe PHY 1-lines each upports 6.0 Gbps data rate and complies to PCI Express base specification 2.1.

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section