Difference between revisions of "MITO 8M SOM/MITO 8M Hardware/Pinout Table"

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−
<section begin="History" />
+
<section begin=History/>
 
{| style="border-collapse:collapse; "
 
{| style="border-collapse:collapse; "
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
|-  
 
|-  
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
|-
 
|-
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|10368|2020/09/29}}
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Sep 2020
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
 
|-
 
|-
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/02/02
 
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pull-up/down information
 
 
|-
 
|-
 
|}
 
|}
−
<section end="History" />
+
<section end=History/>
−
<section begin="Body" />
+
<section begin=Body/>
−
==Connectors and Pinout Table description==
+
==Pinout Table==
 +
===Introduction===
  
−
=== Connectors description ===
+
This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.
−
In the following table are described all available connectors integrated on MITO 8M SOM:
 
−
{| class="wikitable"
 
−
|-
 
−
!Connector name
 
−
!Connector Type
 
−
!Notes
 
−
!Carrier board counterpart
 
−
|-
 
−
|J1
 
−
|SODIMM edge connector 204 pin
 
−
|partially compatible with [[AXEL Lite SOM]]
 
−
|TE Connectivity 2-2013289-1
 
−
|-
 
−
|J4
 
−
|ONE PIECE connector single row 25pins
 
−
|
 
−
|SAMTEC FSI-125-03-G-S-AD-TR
 
−
|-
 
−
|J5
 
−
|ONE PIECE connector single row 25pins
 
−
|
 
−
|SAMTEC FSI-125-03-G-S-AD-TR
 
−
|}
 
−
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M pinout specifications. See the images below for reference:
 
  
−
[[File:MITO 8M-conn-TOP.png|500px|thumb|MITO 8M TOP view|none]]
+
Each row in the pinout tables contains the following information:
−
[[File:MITO 8M-conn-BOTTOM.png|500px|thumb|MITO 8M BOTTOM view|none]]
 
  
−
Below a detailed description of the pinout, grouped in the following tables:
+
{| class="wikitable" style="width:50%;"
−
* two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge
 
−
* a dedicated tables for J4 one-piece connector
 
−
* a dedicated tables for J5 one-piece connector
 
−
 
 
−
=== Pinout Table description ===
 
−
Each row in the pinout tables contains the following information:
 
−
{| class="wikitable"
 
 
|-
 
|-
 
|'''Pin'''
 
|'''Pin'''
Line 59: Line 28:
 
|-
 
|-
 
|'''Pin Name'''  
 
|'''Pin Name'''  
−
| Pin (signal) name on the MITO 8M connectors
+
| Pin (signal) name on the AxelLite connectors
 
|-
 
|-
 
|'''Internal<br>connections'''  
 
|'''Internal<br>connections'''  
−
| Connections to the components
+
| Connections to the Axel Ultra components
 
* CPU.<x> : pin connected to CPU pad named <x>
 
* CPU.<x> : pin connected to CPU pad named <x>
−
* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210)
+
* PMIC.<x> : pin connected to the Power Manager IC
−
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
+
* LAN.<x> : pin connected to the LAN PHY
−
* BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
+
* BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge
 +
* SV.<x>: pin connected to voltage supervisor
 
|-
 
|-
 
|'''Ball/pin #'''  
 
|'''Ball/pin #'''  
Line 100: Line 70:
 
|}
 
|}
  
−
==SODIMM J1 ODD pins declaration ==
+
===Pinout Table ODD pins declaration ===
  
−
{| class="wikitable"
+
{| class="wikitable"  
 
! latexfontsize="scriptsize" | Pin  
 
! latexfontsize="scriptsize" | Pin  
 
! latexfontsize="scriptsize" | Pin Name
 
! latexfontsize="scriptsize" | Pin Name
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Ball/pin #  
 
! latexfontsize="scriptsize" | Ball/pin #  
−
! latexfontsize="scriptsize" |Voltage domain
+
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Notes
 
! latexfontsize="scriptsize" | Notes
Line 116: Line 86:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 178: Line 148:
 
|NVCC_1V8
 
|NVCC_1V8
 
|I/O
 
|I/O
−
|Must be level translated if used @ 3V3
+
|must be level translated if used @ 3V3
−
Internally pulled-up to 1.8V during bootstrap
 
 
|
 
|
 
|
 
|
Line 189: Line 158:
 
|NVCC_1V8
 
|NVCC_1V8
 
|I/O
 
|I/O
−
|Must be level translated if used @ 3V3
+
|must be level translated if used @ 3V3
−
Internally pulled-up to 1.8V during bootstrap
 
 
|
 
|
 
|
 
|
Line 319: Line 287:
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
−
| rowspan="4" |Internally used for ETH PHY reset, do not connect
+
| rowspan="4" |
 
|ALT0
 
|ALT0
 
|GPIO1_IO01
 
|GPIO1_IO01
Line 354: Line 322:
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
−
| rowspan="3" |Internally used, do not connect
+
| rowspan="3" |
 
|ALT0
 
|ALT0
 
|GPIO1_IO13
 
|GPIO1_IO13
Line 458: Line 426:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 486: Line 454:
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
−
| rowspan="3" |Internally used for MIPI-to-LVDS interrupt, do not connect
+
| rowspan="3" |
−
Pulled-up to NVCC_3V3
 
 
|ALT0
 
|ALT0
 
|GPIO1_IO05
 
|GPIO1_IO05
Line 535: Line 502:
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
−
| rowspan="4" |Internally used for MIPI-to-LVDS enable, do not connect
+
| rowspan="4" |
 
|ALT0
 
|ALT0
 
|GPIO1_IO06
 
|GPIO1_IO06
Line 584: Line 551:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 672: Line 639:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 818: Line 785:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 928: Line 895:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 1,038: Line 1,005:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 1,148: Line 1,115:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 1,237: Line 1,204:
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
−
| rowspan="3" |used as default Linux console
+
| rowspan="6" |used as default Linux console
 
|ALT0
 
|ALT0
 
|UART2_TX
 
|UART2_TX
Line 1,253: Line 1,220:
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
−
| rowspan="3" |used as default Linux console
 
 
|ALT0
 
|ALT0
 
|UART2_RXD
 
|UART2_RXD
Line 1,366: Line 1,332:
 
|DGND
 
|DGND
 
| -
 
| -
−
| -
+
|<nowiki>-</nowiki>
 
|G
 
|G
 
|
 
|
Line 1,374: Line 1,340:
 
|}
 
|}
  
−
==SODIMM J1 EVEN  pins declaration ==
+
===Pinout Table EVEN  pins declaration ===
  
 
{| class="wikitable"  
 
{| class="wikitable"  
Line 1,381: Line 1,347:
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Internal Connections  
 
! latexfontsize="scriptsize" | Ball/pin #  
 
! latexfontsize="scriptsize" | Ball/pin #  
−
! latexfontsize="scriptsize" | Voltage domain  
+
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Notes
 
! latexfontsize="scriptsize" | Notes
Line 1,533: Line 1,499:
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
−
| rowspan="4" |Internally used for SW reset, do not connect
+
| rowspan="4" |
 
|ALT0
 
|ALT0
 
|GPIO1_IO02
 
|GPIO1_IO02
Line 1,757: Line 1,723:
 
|-
 
|-
 
| rowspan="2" |J1.54
 
| rowspan="2" |J1.54
−
| rowspan="2" |GPIO1_IO10
+
| rowspan="2" |SD1_STROBE
−
| rowspan="2" |CPU.GPIO1_IO10
+
| rowspan="2" |CPU.SD1_STROBE
−
| rowspan="2" |M7
+
| rowspan="2" |T24
−
| rowspan="2" |NVCC_3V3
+
| rowspan="2" |NVCC_1V8
 +
(NVCC_3V3 on request)
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
−
| rowspan="2" |Internally used for ETH PHY interrupt, do not connect
+
| rowspan="2" |internally used for eMMC
 +
(available on NAND storage SOM) ???
 
|ALT0
 
|ALT0
−
|GPIO1_IO10
+
|USDHC1_STROBE
 
|-
 
|-
−
|ALT1
+
|ALT5
−
|USB1_OTG_ID
+
|GPIO2_IO11
 
|-
 
|-
 
|J1.56
 
|J1.56
Line 2,011: Line 1,979:
 
|VDDA_1V8
 
|VDDA_1V8
 
|D
 
|D
−
|Internally used for PCIe CLK, do not connect
+
|
 
|
 
|
 
|
 
|
Line 2,021: Line 1,989:
 
|VDDA_1V8
 
|VDDA_1V8
 
|D
 
|D
−
|Internally used for PCIe CLK, do not connect
+
|
 
|
 
|
 
|
 
|
Line 2,206: Line 2,174:
 
|-
 
|-
 
|J1.124
 
|J1.124
−
(NAND on board)
 
 
|NAND_DQS
 
|NAND_DQS
 
|CPU.NAND_DQS
 
|CPU.NAND_DQS
Line 2,212: Line 2,179:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
−
|Internally used for NAND, do not connect
+
|internally used for NAND
 
|
 
|
 
|
 
|
−
|-
 
−
| rowspan="3" |J1.124
 
−
(eMMC on board)
 
−
| rowspan="3" |NAND_DQS
 
−
| rowspan="3" |CPU.NAND_DQS
 
−
| rowspan="3" |M20
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_DQS
 
−
|-
 
−
|ALT1
 
−
|QSPI_A_DQS
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO14
 
 
|-
 
|-
 
|J1.126
 
|J1.126
−
(NAND on board)
 
 
|NAND_ALE
 
|NAND_ALE
 
|CPU.NAND_ALE
 
|CPU.NAND_ALE
Line 2,240: Line 2,189:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
−
|Internally used for NAND, do not connect
+
|internally used for NAND
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="3" |J1.126
+
|J1.128
−
(eMMC on board)
+
|NAND_CE0_B  //  SD1_CLK
−
| rowspan="3" |NAND_ALE
+
|CPU.NAND_CE0_B // CPU.SD1_CLK
−
| rowspan="3" |CPU.NAND_ALE
+
|H19  //  L25
−
| rowspan="3" |G19
+
|NVCC_1V8  //  NVCC_3V3 ???
−
| rowspan="3" |NVCC_3V3
+
|I/O
−
| rowspan="3" |I/O
+
|???
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_ALE
 
 
|-
 
|-
−
|ALT1
+
|J1.130
−
|QSPI_A_SCLK
+
|NAND_CE1_B  //  SD1_CMD
 +
|CPU.NAND_CE1_B // CPU.SD1_CMD
 +
|G21  //  L24
 +
|NVCC_1V8  //  NVCC_3V3 ???
 +
|I/O
 +
|???
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.132
−
|GPIO3_IO00
+
|NAND_CE2_B  //  SD1_RST_B
 +
|CPU.NAND_CE2_B // CPU.SD1_RST_B
 +
|F21  //  R24
 +
|NVCC_1V8  //  NVCC_3V3 ???
 +
|I/O
 +
|???
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.128
+
|J1.134
−
(NAND on board)
+
|NAND_CE3_B  //  SD1_STROBE
−
| rowspan="2" |SD1_CLK
+
|CPU.NAND_CE3_B // CPU.SD1_STROBE
−
| rowspan="2" |CPU.SD1_CLK
+
|H20  //  T24
−
| rowspan="2" |L25
+
|NVCC_1V8  //  NVCC_3V3 ???
−
| rowspan="2" |NVCC_3V3
+
|I/O
−
(NVCC_1V8 on request)
+
|???
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_CLK
 
 
|-
 
|-
−
|ALT5
+
|J1.136
−
|GPIO2_IO00
+
|NAND_CLE
 +
|DGND
 +
|H21
 +
|NVCC_3V3
 +
|I/O
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="3" |J1.128
+
|J1.138
−
(eMMC on board)
+
|NAND_DATA00  //  SD1_DATA0
−
| rowspan="3" |NAND_CE0_B
+
|CPU.NAND_DATA00 // CPU.SD1_DATA0
−
| rowspan="3" |CPU.NAND_CE0_B
+
|G20  //  M25
−
| rowspan="3" |H19
+
|NVCC_1V8  //  NVCC_3V3 ???
−
| rowspan="3" |NVCC_3V3
+
|I/O
−
| rowspan="3" |I/O
+
|???
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_CE0_B
 
 
|-
 
|-
−
|ALT1
+
|J1.140
−
|QSPI_A_SS0_B
+
|NAND_DATA01  //  SD1_DATA1
 +
|CPU.NAND_DATA01 // CPU.SD1_DATA1
 +
|J20  //  M24
 +
|NVCC_1V8  //  NVCC_3V3 ???
 +
|I/O
 +
|???
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.142
−
|GPIO3_IO01
+
|NAND_DATA02  //  SD1_DATA2
 +
|CPU.NAND_DATA02 // CPU.SD1_DATA2
 +
|H22  //  N25
 +
|NVCC_1V8  //  NVCC_3V3 ???
 +
|I/O
 +
|???
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.130
+
|J1.144
−
(NAND on board)
+
|NAND_DATA03  //  SD1_DATA3
−
| rowspan="2" |SD1_CMD
+
|CPU.NAND_DATA03 // CPU.SD1_DATA3
−
| rowspan="2" |CPU.SD1_CMD
+
|J21  //  P25
−
| rowspan="2" |L24
+
|NVCC_1V8  //  NVCC_3V3 ???
−
| rowspan="2" |NVCC_3V3
+
|I/O
−
(NVCC_1V8 on request)
+
|???
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_CMD
 
 
|-
 
|-
−
|ALT5
+
|J1.146
−
|GPIO2_IO01
+
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="3" |J1.130
+
|J1.148
−
(eMMC on board)
+
|NAND_DATA04  //  SD1_DATA4
−
| rowspan="3" |NAND_CE1_B
+
|CPU.NAND_DATA04 // CPU.SD1_DATA4
−
| rowspan="3" |CPU.NAND_CE1_B
+
|L20  //  N24
−
| rowspan="3" |G21
+
|NVCC_1V8  //  NVCC_3V3 ???
−
| rowspan="3" |NVCC_3V3
+
|I/O
−
| rowspan="3" |I/O
+
|???
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_CE1_B
 
 
|-
 
|-
−
|ALT1
+
|J1.150
−
|QSPI_A_SS1_B
+
|NAND_DATA05  //  SD1_DATA5
 +
|CPU.NAND_DATA05 // CPU.SD1_DATA5
 +
|J22  //  P24
 +
|NVCC_1V8  //  NVCC_3V3 ???
 +
|I/O
 +
|???
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.152
−
|GPIO3_IO02
+
|NAND_DATA06  //  SD1_DATA6
 +
|CPU.NAND_DATA06 // CPU.SD1_DATA6
 +
|L19  //  R25
 +
|NVCC_1V8  //  NVCC_3V3 ???
 +
|I/O
 +
|???
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.132
+
|J1.154
−
(NAND on board)
+
|NAND_DATA07  //  SD1_DATA7
−
| rowspan="2" |SD1_RST_B
+
|CPU.NAND_DATA07 // CPU.SD1_DATA7
−
| rowspan="2" |CPU.SD1_RST_B
+
|M19  //  T25
−
| rowspan="2" |R24
+
|NVCC_1V8  //  NVCC_3V3 ???
−
| rowspan="2" |NVCC_3V3
+
|I/O
−
(NVCC_1V8 on request)
+
|???
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_RESET_B
 
 
|-
 
|-
−
|ALT5
+
|J1.156
−
|GPIO2_IO10
+
|NAND_RE_B
−
|-
+
|CPU.NAND_RE_B
−
| rowspan="3" |J1.132
+
|K19
−
(eMMC on board)
 
−
| rowspan="3" |NAND_CE2_B
 
−
| rowspan="3" |CPU.NAND_CE2_B
 
−
| rowspan="3" |F21
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_CE2_B
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_SS0_B
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO03
 
−
|-
 
−
| rowspan="2" |J1.134
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_STROBE
 
−
| rowspan="2" |CPU.SD1_STROBE
 
−
| rowspan="2" |T24
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_STROBE
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO11
 
−
|-
 
−
| rowspan="3" |J1.134
 
−
(eMMC on board)
 
−
| rowspan="3" |NAND_CE3_B
 
−
| rowspan="3" |CPU.NAND_CE3_B
 
−
| rowspan="3" |H20
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_CE3_B
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_SS1_B
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO034
 
−
|-
 
−
|J1.136
 
−
(NAND on board)
 
−
|NAND_CLE
 
−
|CPU.NAND_CLE
 
−
|H21
 
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
−
|Internally used for NAND, do not connect
+
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="3" |J1.136
+
|J1.158
−
(eMMC on board)
+
|NAND_READY_B
−
| rowspan="3" |NAND_CLE
+
|CPU.NAND_READY_B
−
| rowspan="3" |CPU.NAND_CLE
+
|K20
−
| rowspan="3" |H21
+
|NVCC_3V3
−
| rowspan="3" |NVCC_3V3
+
|I/O
−
| rowspan="3" |I/O
+
|
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_CLE
 
 
|-
 
|-
−
|ALT1
+
|J1.160
−
|QSPI_B_SCLK
+
|NAND_WE_B
 +
|CPU.NAND_WE_B
 +
|K22
 +
|NVCC_3V3
 +
|I/O
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.162
−
|GPIO3_IO05
+
|NAND_WP_B
 +
|CPU.NAND_WP_B
 +
|K21
 +
|NVCC_3V3
 +
|I/O
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.138
+
|J1.164
−
(NAND on board)
+
|DGND
−
| rowspan="2" |SD1_DATA0
+
|DGND
−
| rowspan="2" |CPU.SD1_DATA0
+
| -
−
| rowspan="2" |M25
+
|<nowiki>-</nowiki>
−
| rowspan="2" |NVCC_3V3
+
|G
−
(NVCC_1V8 on request)
+
|
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_DATA0
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO02
 
 
|-
 
|-
−
| rowspan="3" |J1.138
+
|J1.166
−
(eMMC on board)
+
|CLK1_N
−
| rowspan="3" |NAND_DATA00
+
|CPU.CLK1_N
−
| rowspan="3" |CPU.NAND_DATA00
+
|T23
−
| rowspan="3" |G20
+
|
−
| rowspan="3" |NVCC_3V3
+
|D
−
| rowspan="3" |I/O
+
|
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_DATA00
 
 
|-
 
|-
−
|ALT1
+
|J1.168
−
|QSPI_A_DATA0
+
|CLK1_P
 +
|CPU.CLK1_P
 +
|R23
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.170
−
|GPIO3_IO06
+
|USB2_RXN
−
|-
+
|CPU.USB2_RX_N
−
| rowspan="2" |J1.140
+
|B8
−
(NAND on board)
+
|
−
| rowspan="2" |SD1_DATA1
+
|D
−
| rowspan="2" |CPU.SD1_DATA1
+
|
−
| rowspan="2" |M24
+
|
−
| rowspan="2" |NVCC_3V3
+
|
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA1
 
 
|-
 
|-
−
|ALT5
+
|J1.172
−
|GPIO2_IO0
+
|USB2_RXP
 +
|CPU.USB2_RX_P
 +
|A8
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="3" |J1.140
+
|J1.174
−
(eMMC on board)
+
|USB2_TXN
−
| rowspan="3" |NAND_DATA01
+
|CPU.USB2_TX_N
−
| rowspan="3" |CPU.NAND_DATA01
+
|B9
−
| rowspan="3" |J20
+
|
−
| rowspan="3" |NVCC_3V3
+
|D
−
| rowspan="3" |I/O
+
|
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_DATA01
 
 
|-
 
|-
−
|ALT1
+
|J1.176
−
|QSPI_A_DATA1
+
|USB2_TXP
−
|-
+
|CPU.USB2_TX_P
−
|ALT5
+
|A9
−
|GPIO3_IO07
+
|
−
|-
+
|D
−
| rowspan="2" |J1.142
+
|
−
(NAND on board)
+
|
−
| rowspan="2" |SD1_DATA2
+
|
−
| rowspan="2" |CPU.SD1_DATA2
 
−
| rowspan="2" |N25
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA2
 
 
|-
 
|-
−
|ALT5
+
|J1.178
−
|GPIO2_IO04
+
|USB1_RXN
 +
|CPU.USB1_RX_N
 +
|B12
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="3" |J1.142
+
|J1.180
−
(eMMC on board)
+
|USB1_RXP
−
| rowspan="3" |NAND_DATA02
+
|CPU.USB1_RX_P
−
| rowspan="3" |CPU.NAND_DATA02
+
|A12
−
| rowspan="3" |H22
+
|
−
| rowspan="3" |NVCC_3V3
+
|D
−
| rowspan="3" |I/O
+
|
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_DATA02
 
 
|-
 
|-
−
|ALT1
+
|J1.182
−
|QSPI_A_DATA2
+
|USB1_TXN
−
|-
+
|CPU.USB1_TX_N
−
|ALT5
+
|B13
−
|GPIO3_IO08
+
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.144
+
|J1.184
−
(NAND on board)
+
|USB1_TXP
−
| rowspan="2" |SD1_DATA3
+
|CPU.USB1_TX_P
−
| rowspan="2" |CPU.SD1_DATA3
+
|A13
−
| rowspan="2" |P25
+
|
−
| rowspan="2" |NVCC_3V3
+
|D
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA3
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO05
 
−
|-
 
−
| rowspan="3" |J1.144
 
−
(eMMC on board)
 
−
| rowspan="3" |NAND_DATA03
 
−
| rowspan="3" |CPU.NAND_DATA03
 
−
| rowspan="3" |J21
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_DATA03
 
−
|-
 
−
|ALT1
 
−
|QSPI_A_DATA3
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO09
 
−
|-
 
−
|J1.146
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="2" |J1.148
+
|J1.186
−
(NAND on board)
+
|USB1_VBUS
−
| rowspan="2" |SD1_DATA4
+
|CPU.USB1_VBUS
−
| rowspan="2" |CPU.SD1_DATA4
+
|D14
−
| rowspan="2" |N24
+
| -
−
| rowspan="2" |NVCC_3V3
+
|S
−
(NVCC_1V8 on request)
+
|
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_DATA4
 
 
|-
 
|-
−
|ALT5
+
|J1.188
−
|GPIO2_IO06
+
|USB2_VBUS
 +
|CPU.USB2_VBUS
 +
|D9
 +
| -
 +
|S
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="3" |J1.148
+
|J1.190
−
(eMMC on board)
+
|DGND
−
| rowspan="3" |NAND_DATA04
+
|DGND
−
| rowspan="3" |CPU.NAND_DATA04
+
| -
−
| rowspan="3" |L20
+
|<nowiki>-</nowiki>
−
| rowspan="3" |NVCC_3V3
+
|G
−
| rowspan="3" |I/O
+
|
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_DATA04
 
 
|-
 
|-
−
|ALT1
+
|J1.192
−
|QSPI_B_DATA0
+
|USB1_ID
 +
|CPU.USB1_ID
 +
|C14
 +
|VDD_PHY_3V3
 +
|I
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.194
−
|GPIO3_IO10
+
|USB2_ID
 +
|CPU.USB2_ID
 +
|C9
 +
|VDD_PHY_3V3
 +
|I
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.150
+
|J1.196
−
(NAND on board)
+
|USB1_DN
−
| rowspan="2" |SD1_DATA5
+
|CPU.USB1_DN
−
| rowspan="2" |CPU.SD1_DATA5
+
|B14
−
| rowspan="2" |P24
+
| -
−
| rowspan="2" |NVCC_3V3
+
|D
−
(NVCC_1V8 on request)
+
|
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_DATA5
 
 
|-
 
|-
−
|ALT5
+
|J1.198
−
|GPIO2_IO07
+
|USB1_DP
−
|-
+
|CPU.USB1_DP
−
| rowspan="3" |J1.150
+
|A14
−
(eMMC on board)
+
| -
−
| rowspan="3" |NAND_DATA05
+
|D
−
| rowspan="3" |CPU.NAND_DATA05
+
|
−
| rowspan="3" |J22
+
|
−
| rowspan="3" |NVCC_3V3
+
|
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_DATA05
 
 
|-
 
|-
−
|ALT1
+
|J1.200
−
|QSPI_B_DATA1
+
|USB2_DP
 +
|CPU.USB2_DP
 +
|A10
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.202
−
|GPIO3_IO11
+
|USB2_DN
 +
|CPU.USB2_DN
 +
|B10
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.152
+
|J1.204
−
(NAND on board)
+
|DGND
−
| rowspan="2" |SD1_DATA6
+
|DGND
−
| rowspan="2" |CPU.SD1_DATA6
+
| -
−
| rowspan="2" |R25
+
|<nowiki>-</nowiki>
−
| rowspan="2" |NVCC_3V3
+
|G
−
(NVCC_1V8 on request)
+
|
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_DATA6
 
 
|-
 
|-
−
|ALT5
+
|}
−
|GPIO2_IO08
+
 
 +
===Pinout Table J4 pins declaration ===
 +
{| class="wikitable"
 +
! latexfontsize="scriptsize" | Pin
 +
! latexfontsize="scriptsize" | Pin Name
 +
! latexfontsize="scriptsize" | Internal Connections
 +
! latexfontsize="scriptsize" | Ball/pin #
 +
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
 +
! latexfontsize="scriptsize" | Type
 +
! latexfontsize="scriptsize" | Notes
 +
! latexfontsize="scriptsize" | Alternative Functions
 
|-
 
|-
−
| rowspan="3" |J1.152
+
|J4.1
−
(eMMC on board)
+
|DGND
−
| rowspan="3" |NAND_DATA06
+
|DGND
−
| rowspan="3" |CPU.NAND_DATA06
+
| -
−
| rowspan="3" |L19
+
|<nowiki>-</nowiki>
−
| rowspan="3" |NVCC_3V3
+
|G
−
| rowspan="3" |I/O
+
|
−
| rowspan="3" |
+
|
−
|ALT0
 
−
|RAWNAND_DATA06
 
 
|-
 
|-
−
|ALT1
+
|J4.2
−
|QSPI_B_DATA2
+
|SAI1_RXD7
 +
|CPU.SAI1_RXD7
 +
|G1
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 +
|
 
|-
 
|-
−
|ALT5
+
|J4.3
−
|GPIO3_IO12
+
|SAI1_RXD6
 +
|CPU.SAI1_RXD6
 +
|G2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.154
+
|J4.4
−
(NAND on board)
+
|SAI1_RXD5
−
| rowspan="2" |SD1_DATA7
+
|CPU.SAI1_RXD5
−
| rowspan="2" |CPU.SD1_DATA7
+
|F1
−
| rowspan="2" |T25
+
|NVCC_3V3
−
| rowspan="2" |NVCC_3V3
+
|I/O
−
(NVCC_1V8 on request)
+
|internally used for BOOT config
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|-
−
|ALT0
+
|J4.5
−
|USDHC1_DATA7
+
|SAI1_RXD4
 +
|CPU.SAI1_RXD4
 +
|J1
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 +
|
 
|-
 
|-
−
|ALT5
+
|J4.6
−
|GPIO2_IO09
+
|SAI1_RXD3
 +
|CPU.SAI1_RXD3
 +
|J2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 +
|
 
|-
 
|-
−
| rowspan="3" |J1.154
+
|J4.7
−
(eMMC on board)
+
|SAI1_RXD2
−
| rowspan="3" |NAND_DATA07
+
|CPU.SAI1_RXD2
−
| rowspan="3" |CPU.NAND_DATA07
+
|H2
−
| rowspan="3" |M19
+
|NVCC_3V3
−
| rowspan="3" |NVCC_3V3
+
|I/O
−
| rowspan="3" |I/O
+
|internally used for BOOT config
−
| rowspan="3" |
+
|
−
|ALT0
 
−
|RAWNAND_DATA07
 
 
|-
 
|-
−
|ALT1
+
|J4.8
−
|QSPI_B_DATA3
+
|SAI1_RXD1
 +
|CPU.SAI1_RXD1
 +
|L2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 +
|
 
|-
 
|-
−
|ALT5
+
|J4.9
−
|GPIO3_IO13
+
|SAI1_RXD0
 +
|CPU.SAI1_RXD0
 +
|K2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 +
|
 
|-
 
|-
−
|J1.156
+
|J4.10
−
(NAND on board)
+
|SAI1_RXC
−
|NAND_RE_B
+
|CPU.SAI1_RXC
−
|CPU.NAND_RE_B
+
|K1
−
|K19
 
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
−
|Internally used for NAND, do not connect
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="3" |J1.156
+
|J4.11
−
(eMMC on board)
+
|SAI1_RXFS
−
| rowspan="3" |NAND_RE_B
+
|CPU.SAI1_RXFS
−
| rowspan="3" |CPU.NAND_RE_B
+
|L1
−
| rowspan="3" |K19
+
|NVCC_3V3
−
| rowspan="3" |NVCC_3V3
+
|I/O
−
| rowspan="3" |I/O
+
|
−
| rowspan="3" |
+
|
−
|ALT0
 
−
|RAWNAND_RE_B
 
 
|-
 
|-
−
|ALT1
+
|J4.12
−
|QSPI_B_DQS
+
|DGND
−
|-
+
|DGND
−
|ALT5
+
| -
−
|GPIO3_IO15
+
|<nowiki>-</nowiki>
−
|-
+
|G
−
|J1.158
 
−
(NAND on board)
 
−
|NAND_READY_B
 
−
|CPU.NAND_READY_B
 
−
|K20
 
−
|NVCC_3V3
 
−
|I/O
 
−
|Internally used for NAND, do not connect
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="2" |J1.158
+
|J4.13
−
(eMMC on board)
+
|SAI1_MCLK
−
| rowspan="2" |NAND_READY_B
+
|CPU.SAI1_MCLK
−
| rowspan="2" |CPU.NAND_READY_B
+
|
−
| rowspan="2" |K20
 
−
| rowspan="2" |NVCC_3V3
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|RAWNAND_READY_B
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO16
 
−
|-
 
−
|J1.160
 
−
(NAND on board)
 
−
|NAND_WE_B
 
−
|CPU.NAND_WE_B
 
−
|K22
 
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
−
|Internally used for NAND, do not connect
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="2" |J1.160
+
|J4.14
−
(eMMC on board)
+
|DGND
−
| rowspan="2" |NAND_WE_B
+
|DGND
−
| rowspan="2" |CPU.NAND_WE_B
 
−
| rowspan="2" |K22
 
−
| rowspan="2" |NVCC_3V3
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|RAWNAND_WE_B
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO17
 
−
|-
 
−
|J1.162
 
−
(NAND on board)
 
−
|NAND_WP_B
 
−
|CPU.NAND_WP_B
 
−
|K21
 
−
|NVCC_3V3
 
−
|I/O
 
−
|Internally used for NAND, do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="2" |J1.162
 
−
(eMMC on board)
 
−
| rowspan="2" |NAND_WP_B
 
−
| rowspan="2" |CPU.NAND_WP_B
 
−
| rowspan="2" |K21
 
−
| rowspan="2" |NVCC_3V3
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|RAWNAND_WP_B
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO18
 
−
|-
 
−
|J1.164
 
−
|DGND
 
−
|DGND
 
 
| -
 
| -
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.166
+
|J4.15
−
|CLK1_N
+
|SAI1_TXFS
−
|CPU.CLK1_N
+
|CPU.SAI1_TXFS
−
|T23
+
|H4
 +
|NVCC_3V3
 +
|I/O
 
|
 
|
−
|D
 
 
|
 
|
 +
|-
 +
|J4.16
 +
|SAI1_TXC
 +
|CPU.SAI1_TXC
 +
|J5
 +
|NVCC_3V3
 +
|I/O
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.168
+
|J4.17
−
|CLK1_P
+
|SAI1_TXD0
−
|CPU.CLK1_P
+
|CPU.SAI1_TXD0
−
|R23
+
|F2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 
|
 
|
−
|D
+
|-
 +
|J4.18
 +
|SAI1_TXD1
 +
|CPU.SAI1_TXD1
 +
|E2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 
|
 
|
 +
|-
 +
|J4.19
 +
|SAI1_TXD2
 +
|CPU.SAI1_TXD2
 +
|B2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 
|
 
|
 +
|-
 +
|J4.20
 +
|SAI1_TXD3
 +
|CPU.SAI1_TXD3
 +
|D1
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 
|
 
|
 
|-
 
|-
−
|J1.170
+
|J4.21
−
|USB2_RXN
+
|SAI1_TXD4
−
|CPU.USB2_RX_N
+
|CPU.SAI1_TXD4
−
|B8
+
|D2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 
|
 
|
−
|D
+
|-
 +
|J4.22
 +
|SAI1_TXD5
 +
|CPU.SAI1_TXD5
 +
|C2
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 
|
 
|
 +
|-
 +
|J4.23
 +
|SAI1_TXD6
 +
|CPU.SAI1_TXD6
 +
|B3
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 
|
 
|
 +
|-
 +
|J4.24
 +
|SAI1_TXD7
 +
|CPU.SAI1_TXD7
 +
|C1
 +
|NVCC_3V3
 +
|I/O
 +
|internally used for BOOT config
 
|
 
|
 
|-
 
|-
−
|J1.172
+
|J4.25
−
|USB2_RXP
+
|DGND
−
|CPU.USB2_RX_P
+
|DGND
−
|A8
+
| -
 +
|<nowiki>-</nowiki>
 +
|G
 
|
 
|
−
|D
 
 
|
 
|
 +
|}
 +
===Pinout Table J5 pins declaration ===
 +
{| class="wikitable"
 +
! latexfontsize="scriptsize" | Pin
 +
! latexfontsize="scriptsize" | Pin Name
 +
! latexfontsize="scriptsize" | Internal Connections
 +
! latexfontsize="scriptsize" | Ball/pin #
 +
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
 +
! latexfontsize="scriptsize" | Type
 +
! latexfontsize="scriptsize" | Notes
 +
! latexfontsize="scriptsize" | Alternative Functions
 +
|-
 +
|J5.1
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.174
+
|J5.2
−
|USB2_TXN
+
|PCIE2_RXN
−
|CPU.USB2_TX_N
+
|CPU.PCIE2_RXN_N
−
|B9
+
|D24
−
|
+
| -
 
|D
 
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.176
+
|J5.3
−
|USB2_TXP
+
|PCIE2_RXP
−
|CPU.USB2_TX_P
+
|CPU.PCIE2_RXN_P
−
|A9
+
|D25
−
|
+
| -
 
|D
 
|D
 
|
 
|
 +
|
 +
|-
 +
|J5.4
 +
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.178
+
|J5.5
−
|USB1_RXN
+
|PCIE2_TXN
−
|CPU.USB1_RX_N
+
|CPU.PCIE2_TXN_N
−
|B12
+
|E24
−
|
+
| -
 
|D
 
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.180
+
|J5.6
−
|USB1_RXP
+
|PCIE2_TXP
−
|CPU.USB1_RX_P
+
|CPU.PCIE2_TXN_P
−
|A12
+
|E25
−
|
+
| -
 
|D
 
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.182
+
|J5.7
−
|USB1_TXN
+
|DGND
−
|CPU.USB1_TX_N
+
|DGND
−
|B13
+
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 
|
 
|
 +
|-
 +
|J5.8
 +
|PCIE2_REF_CLKN
 +
|CPU.PCIE2_REF_PAD_CLK_N
 +
|F24
 +
| -
 
|D
 
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.184
+
|J5.9
−
|USB1_TXP
+
|PCIE2_REF_CLKP
−
|CPU.USB1_TX_P
+
|CPU.PCIE2_REF_PAD_CLK_P
−
|A13
+
|F25
−
|
+
| -
 
|D
 
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.186
+
|J5.10
−
|USB1_VBUS
+
|DGND
−
|CPU.USB1_VBUS
+
|DGND
−
|D14
 
 
| -
 
| -
−
|S
+
|<nowiki>-</nowiki>
−
|Absolute maximum ratings 5.25V
+
|G
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.188
+
|J5.11
−
|USB2_VBUS
+
|CSI_P2_CKN
−
|CPU.USB2_VBUS
+
|CPU.MIPI_CSI2_CLK_N
−
|D9
+
|A19
 +
| -
 +
|D
 +
|
 +
|
 +
|-
 +
|J5.12
 +
|CSI_P2_CKP
 +
|CPU.MIPI_CSI2_CLK_P
 +
|B19
 
| -
 
| -
−
|S
+
|D
−
|Absolute maximum ratings 5.25V
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.190
+
|J5.13
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 2,922: Line 2,946:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.192
+
|J5.14
−
|USB1_ID
+
|CSI_P2_DN0
−
|CPU.USB1_ID
+
|CPU.MIPI_CSI2_D0_N
−
|C14
+
|C20
−
|VDD_PHY_3V3
+
| -
−
|I
+
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.194
+
|J5.15
−
|USB2_ID
+
|CSI_P2_DP0
−
|CPU.USB2_ID
+
|CPU.MIPI_CSI2_D0_P
−
|C9
+
|D10
−
|VDD_PHY_3V3
 
−
|I
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.196
 
−
|USB1_DN
 
−
|CPU.USB1_DN
 
−
|B14
 
 
| -
 
| -
 
|D
 
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.198
+
|J5.16
−
|USB1_DP
+
|CSI_P2_DN1
−
|CPU.USB1_DP
+
|CPU.MIPI_CSI2_D1_N
−
|A14
+
|A20
 
| -
 
| -
 
|D
 
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.200
+
|J5.17
−
|USB2_DP
+
|CSI_P2_DP1
−
|CPU.USB2_DP
+
|CPU.MIPI_CSI2_D1_P
−
|A10
+
|B20
 
| -
 
| -
 
|D
 
|D
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.202
+
|J5.18
−
|USB2_DN
 
−
|CPU.USB2_DN
 
−
|B10
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.204
 
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 2,992: Line 2,991:
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
 
|G
 
|G
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|}
+
|J5.19
−
 
+
|CSI_P2_DN2
−
==ONE PIECE J4 pins declaration ==
+
|CPU.MIPI_CSI2_D2_N
−
{| class="wikitable"
+
|A21
−
! latexfontsize="scriptsize" | Pin
 
−
! latexfontsize="scriptsize" | Pin Name
 
−
! latexfontsize="scriptsize" | Internal Connections
 
−
! latexfontsize="scriptsize" | Ball/pin #
 
−
! latexfontsize="scriptsize" | Voltage domain
 
−
! latexfontsize="scriptsize" | Type
 
−
! latexfontsize="scriptsize" | Notes
 
−
! colspan="2" |Alternative Functions
 
−
|-
 
−
|J4.1
 
−
|DGND
 
−
|DGND
 
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
|D
−
|G
 
−
|
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="7" |J4.2
+
|J5.20
−
| rowspan="7" |SAI1_RXD7
+
|CSI_P2_DP2
−
| rowspan="7" |CPU.SAI1_RXD7
+
|CPU.MIPI_CSI2_D2_P
−
| rowspan="7" |G1
+
|B21
−
| rowspan="7" |NVCC_3V3
+
| -
−
| rowspan="7" |I/O
+
|D
−
| rowspan="7" |Internally used for BOOT config
+
|
−
Could be pulled-up or down during bootstrap.
+
|
−
|ALT0
 
−
|SAI1_RX_DATA7
 
−
|-
 
−
|ALT1
 
−
|SAI6_MCLK
 
 
|-
 
|-
−
|ALT2
+
|J5.21
−
|SAI1_TX_SYNC
+
|CSI_P2_DN3
 +
|CPU.MIPI_CSI2_D3_N
 +
|C19
 +
| -
 +
|D
 +
|
 +
|
 
|-
 
|-
−
|ALT3
+
|J5.22
−
|SAI1_TX_DATA4
+
|CSI_P2_DP3
 +
|CPU.MIPI_CSI2_D3_P
 +
|D19
 +
| -
 +
|D
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J5.23
−
|CORESIGHT_TRACE7
+
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J5.24
−
|GPIO4_IO09
+
|I2C4_SCL
 +
|CPU.I2C4_SCL
 +
|F8
 +
|NVCC_3V3
 +
|I/O
 +
|
 +
|
 
|-
 
|-
−
|ALT6
+
|J5.25
−
|SRC_BOOT_CFG7
+
|I2C4_SDA
 +
|CPU.I2C4_SDA
 +
|F9
 +
|NVCC_3V3
 +
|I/O
 +
|
 +
|
 +
|}
 +
 
 +
===Pinout Table JD5 pins declaration ===
 +
{| class="wikitable"
 +
! latexfontsize="scriptsize" | Pin
 +
! latexfontsize="scriptsize" | Pin Name
 +
! latexfontsize="scriptsize" | Internal Connections
 +
! latexfontsize="scriptsize" | Ball/pin #
 +
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
 +
! latexfontsize="scriptsize" | Type
 +
! latexfontsize="scriptsize" | Notes
 +
! latexfontsize="scriptsize" | Alternative Functions
 
|-
 
|-
−
| rowspan="6" |J4.3
+
|JD5.1
−
| rowspan="6" |SAI1_RXD6
+
|DGND
−
| rowspan="6" |CPU.SAI1_RXD6
+
|DGND
−
| rowspan="6" |G2
+
| -
−
| rowspan="6" |NVCC_3V3
+
|<nowiki>-</nowiki>
−
| rowspan="6" |I/O
+
|G
−
| rowspan="6" |Internally used for BOOT config
+
|
−
Could be pulled-up or down during bootstrap.
+
|
−
|ALT0
 
−
|SAI1_RX_DATA6
 
 
|-
 
|-
−
|ALT1
+
|JD5.2
−
|SAI6_TX_SYNC
+
|EEPROM_WP
 +
|Internal EEPROM Write Protect
 +
| -
 +
|NVCC_3V3
 +
|I
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|JD5.3
−
|SAI6_RX_SYNC
+
|NC
 +
|Not Connected
 +
| -
 +
| -
 +
|Z
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|JD5.4
−
|CORESIGHT_TRACE6
+
|JTAG_TCK
 +
|CPU.JTAG_TCK
 +
|T5
 +
|NVCC_3V3
 +
|I
 +
|internal pull-up 10k to NVCC_3V3
 +
|
 
|-
 
|-
−
|ALT5
+
|JD5.5
−
|GPIO4_IO08
+
|JTAG_TMS
 +
|CPU.JTAG_TMS
 +
|V5
 +
|NVCC_3V3
 +
|I
 +
|
 +
|
 
|-
 
|-
−
|ALT6
+
|JD5.6
−
|SRC_BOOT_CFG6
+
|JTAG_TDO
 +
|CPU.JTAG_TDO
 +
|U5
 +
|NVCC_3V3
 +
|O
 +
|
 +
|
 
|-
 
|-
−
| rowspan="7" |J4.4
+
|JD5.7
−
| rowspan="7" |SAI1_RXD5
+
|JTAG_TDI
−
| rowspan="7" |CPU.SAI1_RXD5
+
|CPU.JTAG_TDI
−
| rowspan="7" |F1
+
|W5
−
| rowspan="7" |NVCC_3V3
+
|NVCC_3V3
−
| rowspan="7" |I/O
+
|I
−
| rowspan="7" |Internally used for BOOT config
+
|
−
Could be pulled-up or down during bootstrap.
+
|
−
|ALT0
 
−
|SAI1_RX_DATA5
 
 
|-
 
|-
−
|ALT1
+
|JD5.8
−
|SAI6_TX_DATA0
+
|JTAG_nTRST
 +
|CPU.JTAG_TRST_B
 +
|U6
 +
|NVCC_3V3
 +
|I
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|JD5.9
−
|SAI6_RX_DATA0
+
|CPU_PORn
 +
|CPU.POR_B
 +
PMIC.RESETMCU
 +
|W20
 +
3
 +
|NVCC_SNVS
 +
|I/O
 +
|internal pull-up 100k to NVCC_SNVS
 +
|
 
|-
 
|-
−
|ALT3
+
|JD5.10
−
|SAI1_RX_SYNC
+
|NVCC_3V3
−
|-
+
|NVCC_3V3
−
|ALT4
 
−
|CORESIGHT_TRACE5
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO07
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG5
 
−
|-
 
−
| rowspan="6" |J4.5
 
−
| rowspan="6" |SAI1_RXD4
 
−
| rowspan="6" |CPU.SAI1_RXD4
 
−
| rowspan="6" |J1
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_RX_DATA4
 
−
|-
 
−
|ALT1
 
−
|SAI6_TX_BCLK
 
−
|-
 
−
|ALT2
 
−
|SAI6_RX_BCLK
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE4
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO06
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG4
 
−
|-
 
−
| rowspan="5" |J4.6
 
−
| rowspan="5" |SAI1_RXD3
 
−
| rowspan="5" |CPU.SAI1_RXD3
 
−
| rowspan="5" |J2
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_RX_DATA3
 
−
|-
 
−
|ALT1
 
−
|SAI5_RX_DATA3
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE3
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO05
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG3
 
−
|-
 
−
| rowspan="5" |J4.7
 
−
| rowspan="5" |SAI1_RXD2
 
−
| rowspan="5" |CPU.SAI1_RXD2
 
−
| rowspan="5" |H2
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_RX_DATA2
 
−
|-
 
−
|ALT1
 
−
|SAI5_RX_DATA2
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE2
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO04
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG2
 
−
|-
 
−
| rowspan="5" |J4.8
 
−
| rowspan="5" |SAI1_RXD1
 
−
| rowspan="5" |CPU.SAI1_RXD1
 
−
| rowspan="5" |L2
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_RX_DATA1
 
−
|-
 
−
|ALT1
 
−
|SAI5_RX_DATA1
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE1
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO03
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG1
 
−
|-
 
−
| rowspan="5" |J4.9
 
−
| rowspan="5" |SAI1_RXD0
 
−
| rowspan="5" |CPU.SAI1_RXD0
 
−
| rowspan="5" |K2
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_RX_DATA0
 
−
|-
 
−
|ALT1
 
−
|SAI5_RX_DATA0
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE0
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO02
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG0
 
−
|-
 
−
| rowspan="4" |J4.10
 
−
| rowspan="4" |SAI1_RXC
 
−
| rowspan="4" |CPU.SAI1_RXC
 
−
| rowspan="4" |K1
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|SAI1_RX_BCLK
 
−
|-
 
−
|ALT1
 
−
|SAI5_RX_BCLK
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE_CTL
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO01
 
−
|-
 
−
| rowspan="4" |J4.11
 
−
| rowspan="4" |SAI1_RXFS
 
−
| rowspan="4" |CPU.SAI1_RXFS
 
−
| rowspan="4" |L1
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|SAI1_RX_SYNC
 
−
|-
 
−
|ALT1
 
−
|SAI5_RX_SYNC
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE_CLK
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO00
 
−
|-
 
−
|J4.12
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="4" |J4.13
 
−
| rowspan="4" |SAI1_MCLK
 
−
| rowspan="4" |CPU.SAI1_MCLK
 
−
| rowspan="4" |
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|SAI1_MCLK
 
−
|-
 
−
|ALT1
 
−
|SAI5_MCLK
 
−
|-
 
−
|ALT2
 
−
|SAI1_TX_BCLK
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO20
 
−
|-
 
−
|J4.14
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="4" |J4.15
 
−
| rowspan="4" |SAI1_TXFS
 
−
| rowspan="4" |CPU.SAI1_TXFS
 
−
| rowspan="4" |H4
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|SAI1_TX_SYNC
 
−
|-
 
−
|ALT1
 
−
|SAI5_TX_SYNC
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_EVENTO
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO10
 
−
|-
 
−
| rowspan="4" |J4.16
 
−
| rowspan="4" |SAI1_TXC
 
−
| rowspan="4" |CPU.SAI1_TXC
 
−
| rowspan="4" |J5
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|SAI1_TX_BCLK
 
−
|-
 
−
|ALT1
 
−
|SAI5_TX_BCLK
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_EVENTI
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO11
 
−
|-
 
−
| rowspan="5" |J4.17
 
−
| rowspan="5" |SAI1_TXD0
 
−
| rowspan="5" |CPU.SAI1_TXD0
 
−
| rowspan="5" |F2
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_TX_DATA0
 
−
|-
 
−
|ALT1
 
−
|SAI5_TX_DATA0
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE8
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO12
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG8
 
−
|-
 
−
| rowspan="5" |J4.18
 
−
| rowspan="5" |SAI1_TXD1
 
−
| rowspan="5" |CPU.SAI1_TXD1
 
−
| rowspan="5" |E2
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_TX_DATA1
 
−
|-
 
−
|ALT1
 
−
|SAI5_TX_DATA1
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE9
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO13
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG9
 
−
|-
 
−
| rowspan="5" |J4.19
 
−
| rowspan="5" |SAI1_TXD2
 
−
| rowspan="5" |CPU.SAI1_TXD2
 
−
| rowspan="5" |B2
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_TX_DATA2
 
−
|-
 
−
|ALT1
 
−
|SAI5_TX_DATA2
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE10
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO14
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG10
 
−
|-
 
−
| rowspan="5" |J4.20
 
−
| rowspan="5" |SAI1_TXD3
 
−
| rowspan="5" |CPU.SAI1_TXD3
 
−
| rowspan="5" |D1
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_TX_DATA3
 
−
|-
 
−
|ALT1
 
−
|SAI5_TX_DATA3
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE11
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO15
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG11
 
−
|-
 
−
| rowspan="6" |J4.21
 
−
| rowspan="6" |SAI1_TXD4
 
−
| rowspan="6" |CPU.SAI1_TXD4
 
−
| rowspan="6" |D2
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_TX_DATA4
 
−
|-
 
−
|ALT1
 
−
|SAI6_RX_BCLK
 
−
|-
 
−
|ALT2
 
−
|SAI6_TX_BCLK
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE12
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO16
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG12
 
−
|-
 
−
| rowspan="6" |J4.22
 
−
| rowspan="6" |SAI1_TXD5
 
−
| rowspan="6" |CPU.SAI1_TXD5
 
−
| rowspan="6" |C2
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_TX_DATA5
 
−
|-
 
−
|ALT1
 
−
|SAI6_RX_DATA0
 
−
|-
 
−
|ALT2
 
−
|SAI6_TX_DATA0
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE13
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO17
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG13
 
−
|-
 
−
| rowspan="6" |J4.23
 
−
| rowspan="6" |SAI1_TXD6
 
−
| rowspan="6" |CPU.SAI1_TXD6
 
−
| rowspan="6" |B3
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_TX_DATA6
 
−
|-
 
−
|ALT1
 
−
|SAI6_RX_SYNC
 
−
|-
 
−
|ALT2
 
−
|SAI6_TX_SYNC
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE14
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO18
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG14
 
−
|-
 
−
| rowspan="5" |J4.24
 
−
| rowspan="5" |SAI1_TXD7
 
−
| rowspan="5" |CPU.SAI1_TXD7
 
−
| rowspan="5" |C1
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |Internally used for BOOT config
 
−
Could be pulled-up or down during bootstrap.
 
−
|ALT0
 
−
|SAI1_TX_DATA7
 
−
|-
 
−
|ALT1
 
−
|SAI6_MCLK
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE15
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO19
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG15
 
−
|-
 
−
|J4.25
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|}
 
−
 
 
−
==ONE PIECE J5 pins declaration ==
 
−
{| class="wikitable"
 
−
! latexfontsize="scriptsize" | Pin
 
−
! latexfontsize="scriptsize" | Pin Name
 
−
! latexfontsize="scriptsize" | Internal Connections
 
−
! latexfontsize="scriptsize" | Ball/pin #
 
−
! latexfontsize="scriptsize" | Voltage domain
 
−
! latexfontsize="scriptsize" | Type
 
−
! latexfontsize="scriptsize" | Notes
 
−
! colspan="2" |Alternative Functions
 
−
|-
 
−
|J5.1
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.2
 
−
|PCIE2_RXN
 
−
|CPU.PCIE2_RXN_N
 
−
|D24
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.3
 
−
|PCIE2_RXP
 
−
|CPU.PCIE2_RXN_P
 
−
|D25
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.4
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.5
 
−
|PCIE2_TXN
 
−
|CPU.PCIE2_TXN_N
 
−
|E24
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.6
 
−
|PCIE2_TXP
 
−
|CPU.PCIE2_TXN_P
 
−
|E25
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.7
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.8
 
−
|PCIE2_REF_CLKN
 
−
|CPU.PCIE2_REF_PAD_CLK_N
 
−
|F24
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.9
 
−
|PCIE2_REF_CLKP
 
−
|CPU.PCIE2_REF_PAD_CLK_P
 
−
|F25
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.10
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.11
 
−
|CSI_P2_CKN
 
−
|CPU.MIPI_CSI2_CLK_N
 
−
|A19
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.12
 
−
|CSI_P2_CKP
 
−
|CPU.MIPI_CSI2_CLK_P
 
−
|B19
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.13
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.14
 
−
|CSI_P2_DN0
 
−
|CPU.MIPI_CSI2_D0_N
 
−
|C20
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.15
 
−
|CSI_P2_DP0
 
−
|CPU.MIPI_CSI2_D0_P
 
−
|D10
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.16
 
−
|CSI_P2_DN1
 
−
|CPU.MIPI_CSI2_D1_N
 
−
|A20
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.17
 
−
|CSI_P2_DP1
 
−
|CPU.MIPI_CSI2_D1_P
 
−
|B20
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.18
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.19
 
−
|CSI_P2_DN2
 
−
|CPU.MIPI_CSI2_D2_N
 
−
|A21
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.20
 
−
|CSI_P2_DP2
 
−
|CPU.MIPI_CSI2_D2_P
 
−
|B21
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.21
 
−
|CSI_P2_DN3
 
−
|CPU.MIPI_CSI2_D3_N
 
−
|C19
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.22
 
−
|CSI_P2_DP3
 
−
|CPU.MIPI_CSI2_D3_P
 
−
|D19
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J5.23
 
−
|DGND
 
−
|DGND
 
 
| -
 
| -
 
|<nowiki>-</nowiki>
 
|<nowiki>-</nowiki>
−
|G
+
|S
 
|
 
|
 
|
 
|
−
|
 
−
|-
 
−
| rowspan="4" |J5.24
 
−
| rowspan="4" |I2C4_SCL
 
−
| rowspan="4" |CPU.I2C4_SCL
 
−
| rowspan="4" |F8
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|I2C4_SCL
 
−
|-
 
−
|ALT1
 
−
|PWM2_OUT
 
−
|-
 
−
|ALT2
 
−
|PCIE1_CLKREQ_B
 
−
|-
 
−
|ALT5
 
−
|GPIO5_IO20
 
−
|-
 
−
| rowspan="4" |J5.25
 
−
| rowspan="4" |I2C4_SDA
 
−
| rowspan="4" |CPU.I2C4_SDA
 
−
| rowspan="4" |F9
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|I2C4_SDA
 
−
|-
 
−
|ALT1
 
−
|PWM1_OUT
 
−
|-
 
−
|ALT2
 
−
|PCIE2_CLKREQ_B
 
−
|-
 
−
|ALT5
 
−
|GPIO5_IO21
 
 
|}
 
|}
  

Revision as of 15:36, 24 September 2020

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History
Version Issue Date Notes
1.0.0 Sep 2020 First release


Pinout Table[edit | edit source]

Introduction[edit | edit source]

This chapter contains the pinout description of the MITO 8M module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM MITO 8M connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AxelLite connectors
Internal
connections 		Connections to the Axel Ultra components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC
  • LAN.<x> : pin connected to the LAN PHY
  • BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge
  • SV.<x>: pin connected to voltage supervisor
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH0_LED1 LAN.LED1/PME_N1 17 NVCC_1V8 I/O must be level translated if used @ 3V3
J1.15 ETH0_LED2 LAN.LED2 15 NVCC_1V8 I/O must be level translated if used @ 3V3
J1.17 DGND DGND - - G
J1.19 ETH0_TXRX0_P LAN.TXRXP_A 2 - D
J1.21 ETH0_TXRX0_M LAN.TXRXM_A 3 - D
J1.23 ETH0_TXRX1_P LAN.TXRXP_B 5 - D
J1.25 ETH0_TXRX1_M LAN.TXRXM_B 6 - D
J1.27 ETH0_TXRX2_P LAN.TXRXP_C 7 - D
J1.29 ETH0_TXRX2_M LAN.TXRXM_C 8 - D
J1.31 ETH0_TXRX3_P LAN.TXRXP_D 10 - D
J1.33 ETH0_TXRX3_M LAN.TXRXM_D 11 - D
J1.35 DGND DGND - - G
J1.37 GPIO1_IO00 CPU.GPIO1_IO00 T6 NVCC_3V3 I/O ALT0 GPIO1_IO00
ALT1 CCM_ENET_PHY_REF_CLK_ROOT
ALT5 ANAMIX_REF_CLK_32K
ALT6 CCM_EXT_CLK1
J1.39 GPIO1_IO01 CPU.GPIO1_IO01 T7 NVCC_3V3 I/O ALT0 GPIO1_IO01
ALT1 PWM1_OUT
ALT5 ANAMIX_REF_CLK_25M
ALT6 CCM_EXT_CLK2
J1.41 SPDIF_EXT_CLK CPU.SPDIF_EXT_CLK E6 NVCC_3V3 I/O ALT0 SPDIF1_EXT_CLK
ALT1 PWM1_OUT
ALT5 GPIO5_IO05
J1.43 GPIO1_IO13 CPU.GPIO1_IO13 K6 NVCC_3V3 I/O ALT0 GPIO1_IO13
ALT1 USB1_OTG_OC
ALT5 PWM2_OUT
J1.45 VDD_PHY_1V8
J1.47 ECSPI2_SCLK CPU.ECSPI2_SCLK C5 NVCC_3V3 I/O ALT0 ECSPI2_SCLK
ALT1 UART4_RX
ALT5 GPIO5_IO10
J1.49 ECSPI2_MOSI CPU.ECSPI2_MOSI E5 NVCC_3V3 I/O ALT0 ECSPI2_MOSI
ALT1 UART4_TX
ALT5 GPIO5_IO11
J1.51 GPIO1_IO08 CPU.GPIO1_IO08 N7 NVCC_3V3 I/O ALT0 GPIO1_IO08
ALT1 ENET1_1588_EVENT0_IN
ALT5 USDHC2_RESET_B
J1.53 GPIO1_IO09 CPU.GPIO1_IO09 M7 NVCC_3V3 I/O ALT0 GPIO1_IO09
ALT1 ENET1_1588_EVENT0_OUT
ALT5 SDMA2_EXT_EVENT0
J1.55 ECSPI2_MISO CPU.ECSPI2_MISO B5 NVCC_3V3 I/O ALT0 ECSPI2_MISO
ALT1 UART4_CTS_B
ALT5 GPIO5_IO12
J1.57 DGND DGND - - G
J1.59 ECSPI2_SS0 CPU.ECSPI2_SS0 A5 NVCC_3V3 I/O ALT0 ECSPI2_SS0
ALT1 UART4_RTS_B
ALT5 GPIO5_IO13
J1.61 GPIO1_IO05 CPU.GPIO1_IO05 P7 NVCC_3V3 I/O ALT0 GPIO1_IO05
ALT1 M4_NMI
ALT5 CCM_PMIC_READY
J1.63 I2C2_SCL CPU.I2C2_SCL G7 NVCC_3V3 I/O ALT0 I2C2_SCL
ALT1 ENET1_1588_EVENT1_IN
ALT5 GPIO5_IO16
J1.65 I2C2_SDA CPU.I2C2_SDA F7 NVCC_3V3 I/O ALT0 I2C2_SDA
ALT1 ENET1_1588_EVENT1_OUT
ALT5 GPIO5_IO17
J1.67 GPIO1_IO06 CPU.GPIO1_IO06 N5 NVCC_3V3 I/O ALT0 GPIO1_IO06
ALT1 ENET1_MDC
ALT5 USDHC1_CD_B
ALT6 CCM_EXT_CLK3
J1.69 SAI2_RXC CPU.SAI2_RXC H3 NVCC_3V3 I/O ALT0 SAI2_RX_BCLK
ALT1 SAI5_TX_BCLK
ALT5 GPIO4_IO22
J1.71 SAI2_RXFS CPU.SAI2_RXFS J4 NVCC_3V3 I/O ALT0 SAI2_RX_SYNC
ALT1 SAI5_TX_SYNC
ALT5 GPIO4_IO21
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 N22 NVCC_3V3 I/O ALT0 USDHC2_DATA0
ALT5 GPIO2_IO15
J1.77 SD2_DATA1 CPU.SD2_DATA1 N21 NVCC_3V3 I/O ALT0 USDHC2_DATA1
ALT5 GPIO2_IO16
J1.79 SD2_DATA2 CPU.SD2_DATA2 P22 NVCC_3V3 I/O ALT0 USDHC2_DATA2
ALT5 GPIO2_IO17
J1.81 SD2_DATA3 CPU.SD2_DATA03 P21 NVCC_3V3 I/O ALT0 USDHC2_DATA3
ALT5 GPIO2_IO18
J1.83 SD2_CMD CPU.SD2_CMD M22 NVCC_3V3 I/O ALT0 USDHC2_CMD
ALT5 GPIO2_IO14
J1.85 SD2_CLK CPU.SD2_CLK L22 NVCC_3V3 I/O ALT0 USDHC2_CLK
ALT5 GPIO2_IO13
J1.87 DGND DGND - - G
J1.89 UART3_TXD CPU.UART3_TXD B7 NVCC_3V3 I/O ALT0 UART3_TX
ALT1 UART1_RTS_B
ALT5 GPIO5_IO27
J1.91 UART3_RXD CPU.UART3_RXD A6 NVCC_3V3 I/O ALT0 UART3_RX
ALT1 UART1_CTS_B
ALT5 GPIO5_IO26
J1.93 UART4_TXD CPU.UART4_TXD D7 NVCC_3V3 I/O ALT0 UART4_TX
ALT1 UART2_RTS_B
ALT2 PCIE2_CLKREQ_B
ALT5 GPIO5_IO29
J1.95 UART4_RXD CPU.UART4_RXD C6 NVCC_3V3 I/O ALT0 UART4_RX
ALT1 UART2_CTS_B
ALT2 PCIE1_CLKREQ_B
ALT5 GPIO5_IO28
J1.97 SD2_WP CPU.SD2_WP M21 NVCC_3V3 I/O ALT0 USDHC2_WP
ALT5 GPIO2_IO20
J1.99 SD2_RST_B CPU.SD2_RESET_B R22 NVCC_3V3 I/O ALT0 USDHC2_RESET_B
ALT5 GPIO2_IO19
J1.101 HDMI_DDC_SCL CPU.HDMI_DDC_SCL R3 VDD_PHY_1V8 I/O
J1.103 HDMI_DDC_SDA CPU.HDMI_DDC_SDA P3 VDD_PHY_1V8 I/O
J1.105 HDMI_AUX_N CPU.HDMI_AUX_N V2 - D connected with capacitor in series
J1.107 HDMI_AUX_P CPU.HDMI_AUX_P V1 - D connected with capacitor in series
J1.109 DGND DGND - - G
J1.111 HDMI_TX_M_LN_3 CPU.HDMI_TX_M_LN_3 M2 - D connected with capacitor in series
J1.113 HDMI_TX_P_LN_3 CPU.HDMI_TX_P_LN_3 M1 - D connected with capacitor in series
J1.115 HDMI_TX_M_LN_0 CPU.HDMI_TX_M_LN_0 T2 - D connected with capacitor in series
J1.117 HDMI_TX_P_LN_0 CPU.HDMI_TX_P_LN_0 T1 - D connected with capacitor in series
J1.119 HDMI_TX_M_LN_1 CPU.HDMI_TX_M_LN_1 U1 - D connected with capacitor in series
J1.121 HDMI_TX_P_LN_1 CPU.HDMI_TX_P_LN_1 U2 - D connected with capacitor in series
J1.123 HDMI_TX_M_LN_2 CPU.HDMI_TX_M_LN_2 N1 - D connected with capacitor in series
J1.125 HDMI_TX_P_LN_2 CPU.HDMI_TX_P_LN_2 N2 - D connected with capacitor in series
J1.127 HDMI_CEC CPU.HDMI_CEC W3 VDD_PHY_1V8 I/O
J1.129 HDMI_HPD CPU.HDMI_HPD W2 VDD_PHY_1V8 I/O
J1.131 DGND DGND - - G
J1.133 LVDS0_CLK_N BRIDGE.A_CLKN F9 - D
J1.135 LVDS0_CLK_P BRIDGE.A_CLKP F8 - D
J1.137 LVDS0_TX0_N BRIDGE.A_Y0N C9 - D
J1.139 LVDS0_TX0_P BRIDGE.A_Y0P C8 - D
J1.141 LVDS0_TX1_N BRIDGE.A_Y1N D9 - D
J1.143 LVDS0_TX1_P BRIDGE.A_Y1P D8 - D
J1.145 LVDS0_TX2_N BRIDGE.A_Y2N E9 - D
J1.147 LVDS0_TX2_P BRIDGE.A_Y2P E8 - D
J1.149 LVDS0_TX3_N BRIDGE.A_Y3N G9 - D
J1.151 LVDS0_TX3_P BRIDGE.A_Y3P G8 - D
J1.153 DGND DGND - - G
J1.155 LVDS1_CLK_N BRIDGE.B_CLKN A6 - D
J1.157 LVDS1_CLK_P BRIDGE.B_CLKP B6 - D
J1.159 LVDS1_TX0_N BRIDGE.B_Y0N A3 - D
J1.161 LVDS1_TX0_P BRIDGE.B_Y0P B3 - D
J1.163 LVDS1_TX1_N BRIDGE.B_Y1N A4 - D
J1.165 LVDS1_TX1_P BRIDGE.B_Y1P B4 - D
J1.167 LVDS1_TX2_N BRIDGE.B_Y2N A5 - D
J1.169 LVDS1_TX2_P BRIDGE.B_Y2P B5 - D
J1.171 LVDS1_TX3_N BRIDGE.B_Y3N A7 - D
J1.173 LVDS1_TX3_P BRIDGE.B_Y3P B7 - D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.SD2_CD_B L21 NVCC_3V3 I/O ALT0 USDHC2_CD_B
ALT5 GPIO2_IO12
J1.179 ECSPI1_SS0 CPU.ECSPI1_SS0 D4 NVCC_3V3 I/O ALT0 ECSPI1_SS0
ALT1 UART3_RTS_B
ALT5 GPIO5_IO09
J1.181 ECSPI1_SCLK CPU.ECSPI1_SCLK D5 NVCC_3V3 I/O ALT0 ECSPI1_SCLK
ALT1 UART3_RX
ALT5 GPIO5_IO06
J1.183 ECSPI1_MISO CPU.ECSPI1_MISO B4 NVCC_3V3 I/O ALT0 ECSPI1_MISO
ALT1 UART3_CTS_B
ALT5 GPIO5_IO08
J1.185 GPIO1_IO03 CPU.GPIO1_IO03 P4 NVCC_3V3 I/O ALT0 GPIO1_IO03
ALT1 USDHC1_VSELECT
ALT5 SDMA1_EXT_EVENT0
J1.187 UART2_TXD CPU.UART2_TXD D6 NVCC_3V3 I/O used as default Linux console ALT0 UART2_TX
ALT1 ECSPI3_SS0
ALT5 GPIO5_IO25
J1.189 UART2_RXD CPU.UART2_RXD B6 NVCC_3V3 I/O ALT0 UART2_RXD
ALT1 ECSPI3_MISO
ALT5 GPIO5_IO24
J1.191 UART1_TXD CPU.UART1_TXD A7 NVCC_3V3 I/O ALT0 UART1_TX
ALT1 ECSPI3_MOSI
ALT5 GPIO5_IO23
J1.193 UART1_RXD CPU.UART1_RXD C7 NVCC_3V3 I/O ALT0 UART1_RXD
ALT1 ECSPI3_SCLK
ALT5 GPIO5_IO22
J1.195 ECSPI1_MOSI CPU.ECSPI1_MOSI A4 NVCC_3V3 I/O ALT0 ECSPI1_MOSI
ALT1 UART3_TX
ALT5 GPIO5_IO07
J1.197 GPIO1_IO14 CPU.GPIO1_IO14 K7 NVCC_3V3 I/O ALT0 GPIO1_IO14
ALT1 USB2_OTG_PWR
ALT5 PWM3_OUT
ALT6 CCM_CLKO1
J1.199 GPIO1_IO04 CPU.GPIO1_IO04 P5 NVCC_3V3 I/O ALT0 GPIO1_IO04
ALT1 USDHC2_VSELECT
ALT5 SDMA1_EXT_EVENT1
J1.201 GPIO1_IO12 CPU.GPIO1_IO12 L7 NVCC_3V3 I/O ALT0 GPIO1_IO12
ALT1 USB1_OTG_PWR
ALT5 SDMA2_EXT_EVENT1
J1.203 DGND DGND - - G

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 PMIC_LICELL PMIC.LICELL 30 - S
J1.16 CPU_ONOFF CPU.ONOFF W21 NVCC_SNVS I internal pull-up 100k to NVCC_SNVS
J1.18 BOARD_PGOOD - - NVCC_3V3 O
J1.20 BOOT_MODE_SEL BOOT MODE SELECTION - NVCC_3V3 I internal pull-up to NVCC_3V3
J1.22 CPU_PORn CPU.POR_B

PMIC.RESETMCU

W20

3

NVCC_SNVS I/O internal pull-up 100k to NVCC_SNVS
J1.24 EXT_RESET MASTER RESET - - I internal pull-up to NVCC_SNVS
J1.26 SAI3_RXC CPU.SAI3_RXC F4 NVCC_3V3 I/O ALT0 SAI3_RX_BCLK
ALT1 GPT1_CAPTURE2
ALT2 SAI5_RX_BCLK
ALT5 GPIO4_IO29
J1.28 GPIO1_IO02 CPU.GPIO1_IO02 R4 NVCC_3V3 I/O ALT0 GPIO1_IO02
ALT1 WDOG1_WDOG_B
ALT5 WDOG1_WDOG_ANY
ALT7 SJC_DE_B
J1.30 DGND DGND - - G
J1.32 SAI3_RXD CPU.SAI3_RXD F3 NVCC_3V3 I/O ALT0 SAI3_RX_DATA0
ALT1 GPT1_COMPARE1
ALT2 SAI5_RX_DATA0
ALT5 GPIO4_IO30
J1.34 SAI2_MCLK CPU.SAI2_MCLK H5 NVCC_3V3 I/O ALT0 SAI2_MCLK
ALT1 SAI5_MCLK
ALT5 GPIO4_IO27
J1.36 SAI3_RXFS CPU.SAI3_RXFS G4 NVCC_3V3 I/O ALT0 SAI3_RX_SYNC
ALT1 GPT1_CAPTURE1
ALT2 SAI5_RX_SYNC
ALT5 GPIO4_IO28
J1.38 I2C3_SCL CPU.I2C3_SCL G8 NVCC_3V3 I/O ALT0 I2C3_SCL
ALT1 PWM4_OUT
ALT2 GPT2_CLK
ALT5 GPIO5_IO18
J1.40 SAI3_TXFS CPU.SAI3_TXFS G3 NVCC_3V3 I/O ALT0 SAI3_TX_SYNC
ALT1 GPT1_CLK
ALT2 SAI5_RX_DATA1
ALT5 GPIO4_IO31
J1.42 SPDIF_RX CPU.SPDIF_RX G6 NVCC_3V3 I/O ALT0 SPDIF1_IN
ALT1 PWM2_OUT
ALT5 GPIO5_IO04
J1.44 SPDIF_TX CPU.SPDIF_TX F6 NVCC_3V3 I/O ALT0 SPDIF1_OUT
ALT1 PWM3_OUT
ALT5 GPIO5_IO03
J1.46 SAI3_MCLK CPU.SAI3_MCLK D3 NVCC_3V3 I/O ALT0 SAI3_MCLK
ALT1 PWM4_OUT
ALT2 SAI5_MCLK
ALT5 GPIO5_IO02
J1.48 I2C3_SDA CPU.I2C3_SDA E9 NVCC_3V3 I/O ALT0 I2C3_SDA
ALT1 PWM3_OUT
ALT2 GPT3_CLK
ALT5 GPIO5_IO19
J1.50 SAI3_TXC CPU.SAI3_TXC C4 NVCC_3V3 I/O ALT0 SAI3_TX_BCLK
ALT1 GPT1_COMPARE2
ALT2 SAI5_RX_DATA2
ALT5 GPIO5_IO00
J1.52 SAI3_TXD CPU.SAI3_TXD C3 NVCC_3V3 I/O ALT0 SAI3_TX_DATA0
ALT1 GPT1_COMPARE3
ALT2 SAI5_RX_DATA3
ALT5 GPIO5_IO01
J1.54 SD1_STROBE CPU.SD1_STROBE T24 NVCC_1V8

(NVCC_3V3 on request)

I/O internally used for eMMC

(available on NAND storage SOM) ???

ALT0 USDHC1_STROBE
ALT5 GPIO2_IO11
J1.56 DGND DGND - - G
J1.58 SAI5_MCLK CPU.SAI5_MCLK K4 NVCC_3V3 I/O ALT0 SAI5_MCLK
ALT1 SAI1_TX_BCLK
ALT2 SAI4_MCLK
ALT5 GPIO3_IO25
J1.60 GPIO1_IO15 CPU.GPIO1_IO15 J6 NVCC_3V3 I/O ALT0 GPIO1_IO15
ALT1 USB2_OTG_OC
ALT5 PWM4_OUT
ALT6 CCM_CLKO2
J1.62 SAI5_RXFS CPU.SAI5_RXFS N4 NVCC_3V3 I/O ALT0 SAI5_RX_SYNC
ALT1 SAI1_TX_DATA0
ALT5 GPIO3_IO19
J1.64 SAI5_RXC CPU.SAI5_RXC L5 NVCC_3V3 I/O ALT0 SAI5_RX_BCLK
ALT1 SAI1_TX_DATA1
ALT5 GPIO3_IO20
J1.66 SAI2_TXC CPU.SAI2_TXC J5 NVCC_3V3 I/O ALT0 SAI2_TX_BCLK
ALT1 SAI5_TX_DATA2
ALT5 GPIO4_IO25
J1.68 SAI2_TXD0 CPU.SAI2_TXD0 G5 NVCC_3V3 I/O ALT0 SAI2_TX_DATA0
ALT1 SAI5_TX_DATA3
ALT5 GPIO4_IO26
J1.70 SAI2_TXFS CPU.SAI2_TXFS H4 NVCC_3V3 I/O ALT0 SAI2_TX_SYNC
ALT1 SAI5_TX_DATA1
ALT5 GPIO4_IO24
J1.72 SAI2_RXD0 CPU.SAI2_RXD0 H6 NVCC_3V3 I/O ALT0 SAI2_RX_DATA0
ALT1 SAI5_TX_DATA0
ALT5 GPIO4_IO23
J1.74 SAI5_RXD0 CPU.SAI5_RXD0 M5 NVCC_3V3 I/O ALT0 SAI5_RX_DATA0
ALT1 SAI1_TX_DATA2
ALT5 GPIO3_IO21
J1.76 SAI5_RXD1 CPU.SAI5_RXD1 L4 NVCC_3V3 I/O ALT0 SAI5_RX_DATA1
ALT1 SAI1_TX_DATA3
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_SYNC
ALT5 GPIO3_IO212
J1.78 SAI5_RXD2 CPU.SAI5_RXD2 M4 NVCC_3V3 I/O ALT0 SAI5_RX_DATA2
ALT1 SAI1_TX_DATA4
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_BCLK
ALT5 GPIO3_IO23
J1.80 SAI5_RXD3 CPU.SAI5_RXD3 K5 NVCC_3V3 I/O ALT0 SAI5_RX_DATA3
ALT1 SAI1_TX_DATA5
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_DATA0
ALT5 GPIO3_IO24
J1.82 DGND DGND - - G
J1.84 CLK2_N CPU.CLK2_N T22 VDDA_1V8 D
J1.86 CLK2_P CPU.CLK2_P U22 VDDA_1V8 D
J1.88 PCIE1_REF_CLKN CPU.PCIE1_REF_PAD_CLK_N K24 VDD_PHY_3V3 D
J1.90 PCIE1_REF_CLKP CPU.PCIE1_REF_PAD_CLK_P K25 VDD_PHY_3V3 D
J1.92 PCIE1_RXN CPU.PCIE1_RXN_N H24 VDD_PHY_3V3 D
J1.94 PCIE1_RXP CPU.PCIE1_RXN_P H25 VDD_PHY_3V3 D
J1.96 PCIE1_TXN CPU.PCIE1_TXN_N J24 VDD_PHY_3V3 D
J1.98 PCIE1_TXP CPU.PCIE1_TXN_P J25 VDD_PHY_3V3 D
J1.100 DGND DGND - - G
J1.102 CSI1_CLK_N CPU.MIPI_CSI1_CLK_N A22 - D
J1.104 CSI1_CLK_P CPU.MIPI_CSI1_CLK_P B22 - D
J1.106 CSI1_D0_N CPU.MIPI_CSI1_D0_N A23 - D
J1.108 CSI1_D0_P CPU.MIPI_CSI1_D0_P B23 - D
J1.110 CSI1_D1_N CPU.MIPI_CSI1_D1_N C22 - D
J1.112 CSI1_D1_P CPU.MIPI_CSI1_D1_P D22 - D
J1.114 CSI1_D2_N CPU.MIPI_CSI1_D2_N B24 - D
J1.116 CSI1_D2_P CPU.MIPI_CSI1_D2_P C23 - D
J1.118 CSI1_D3_N CPU.MIPI_CSI1_D3_N C21 - D
J1.120 CSI1_D3_P CPU.MIPI_CSI1_D3_P D21 - D
J1.122 DGND DGND - - G
J1.124 NAND_DQS CPU.NAND_DQS M20 NVCC_3V3 I/O internally used for NAND
J1.126 NAND_ALE CPU.NAND_ALE G19 NVCC_3V3 I/O internally used for NAND
J1.128 NAND_CE0_B // SD1_CLK CPU.NAND_CE0_B // CPU.SD1_CLK H19 // L25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.130 NAND_CE1_B // SD1_CMD CPU.NAND_CE1_B // CPU.SD1_CMD G21 // L24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.132 NAND_CE2_B // SD1_RST_B CPU.NAND_CE2_B // CPU.SD1_RST_B F21 // R24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.134 NAND_CE3_B // SD1_STROBE CPU.NAND_CE3_B // CPU.SD1_STROBE H20 // T24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.136 NAND_CLE DGND H21 NVCC_3V3 I/O
J1.138 NAND_DATA00 // SD1_DATA0 CPU.NAND_DATA00 // CPU.SD1_DATA0 G20 // M25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.140 NAND_DATA01 // SD1_DATA1 CPU.NAND_DATA01 // CPU.SD1_DATA1 J20 // M24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.142 NAND_DATA02 // SD1_DATA2 CPU.NAND_DATA02 // CPU.SD1_DATA2 H22 // N25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.144 NAND_DATA03 // SD1_DATA3 CPU.NAND_DATA03 // CPU.SD1_DATA3 J21 // P25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.146 DGND DGND - - G
J1.148 NAND_DATA04 // SD1_DATA4 CPU.NAND_DATA04 // CPU.SD1_DATA4 L20 // N24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.150 NAND_DATA05 // SD1_DATA5 CPU.NAND_DATA05 // CPU.SD1_DATA5 J22 // P24 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.152 NAND_DATA06 // SD1_DATA6 CPU.NAND_DATA06 // CPU.SD1_DATA6 L19 // R25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.154 NAND_DATA07 // SD1_DATA7 CPU.NAND_DATA07 // CPU.SD1_DATA7 M19 // T25 NVCC_1V8 // NVCC_3V3 ??? I/O ???
J1.156 NAND_RE_B CPU.NAND_RE_B K19 NVCC_3V3 I/O
J1.158 NAND_READY_B CPU.NAND_READY_B K20 NVCC_3V3 I/O
J1.160 NAND_WE_B CPU.NAND_WE_B K22 NVCC_3V3 I/O
J1.162 NAND_WP_B CPU.NAND_WP_B K21 NVCC_3V3 I/O
J1.164 DGND DGND - - G
J1.166 CLK1_N CPU.CLK1_N T23 D
J1.168 CLK1_P CPU.CLK1_P R23 D
J1.170 USB2_RXN CPU.USB2_RX_N B8 D
J1.172 USB2_RXP CPU.USB2_RX_P A8 D
J1.174 USB2_TXN CPU.USB2_TX_N B9 D
J1.176 USB2_TXP CPU.USB2_TX_P A9 D
J1.178 USB1_RXN CPU.USB1_RX_N B12 D
J1.180 USB1_RXP CPU.USB1_RX_P A12 D
J1.182 USB1_TXN CPU.USB1_TX_N B13 D
J1.184 USB1_TXP CPU.USB1_TX_P A13 D
J1.186 USB1_VBUS CPU.USB1_VBUS D14 - S
J1.188 USB2_VBUS CPU.USB2_VBUS D9 - S
J1.190 DGND DGND - - G
J1.192 USB1_ID CPU.USB1_ID C14 VDD_PHY_3V3 I
J1.194 USB2_ID CPU.USB2_ID C9 VDD_PHY_3V3 I
J1.196 USB1_DN CPU.USB1_DN B14 - D
J1.198 USB1_DP CPU.USB1_DP A14 - D
J1.200 USB2_DP CPU.USB2_DP A10 - D
J1.202 USB2_DN CPU.USB2_DN B10 - D
J1.204 DGND DGND - - G

Pinout Table J4 pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J4.1 DGND DGND - - G
J4.2 SAI1_RXD7 CPU.SAI1_RXD7 G1 NVCC_3V3 I/O internally used for BOOT config
J4.3 SAI1_RXD6 CPU.SAI1_RXD6 G2 NVCC_3V3 I/O internally used for BOOT config
J4.4 SAI1_RXD5 CPU.SAI1_RXD5 F1 NVCC_3V3 I/O internally used for BOOT config
J4.5 SAI1_RXD4 CPU.SAI1_RXD4 J1 NVCC_3V3 I/O internally used for BOOT config
J4.6 SAI1_RXD3 CPU.SAI1_RXD3 J2 NVCC_3V3 I/O internally used for BOOT config
J4.7 SAI1_RXD2 CPU.SAI1_RXD2 H2 NVCC_3V3 I/O internally used for BOOT config
J4.8 SAI1_RXD1 CPU.SAI1_RXD1 L2 NVCC_3V3 I/O internally used for BOOT config
J4.9 SAI1_RXD0 CPU.SAI1_RXD0 K2 NVCC_3V3 I/O internally used for BOOT config
J4.10 SAI1_RXC CPU.SAI1_RXC K1 NVCC_3V3 I/O
J4.11 SAI1_RXFS CPU.SAI1_RXFS L1 NVCC_3V3 I/O
J4.12 DGND DGND - - G
J4.13 SAI1_MCLK CPU.SAI1_MCLK NVCC_3V3 I/O
J4.14 DGND DGND - - G
J4.15 SAI1_TXFS CPU.SAI1_TXFS H4 NVCC_3V3 I/O
J4.16 SAI1_TXC CPU.SAI1_TXC J5 NVCC_3V3 I/O
J4.17 SAI1_TXD0 CPU.SAI1_TXD0 F2 NVCC_3V3 I/O internally used for BOOT config
J4.18 SAI1_TXD1 CPU.SAI1_TXD1 E2 NVCC_3V3 I/O internally used for BOOT config
J4.19 SAI1_TXD2 CPU.SAI1_TXD2 B2 NVCC_3V3 I/O internally used for BOOT config
J4.20 SAI1_TXD3 CPU.SAI1_TXD3 D1 NVCC_3V3 I/O internally used for BOOT config
J4.21 SAI1_TXD4 CPU.SAI1_TXD4 D2 NVCC_3V3 I/O internally used for BOOT config
J4.22 SAI1_TXD5 CPU.SAI1_TXD5 C2 NVCC_3V3 I/O internally used for BOOT config
J4.23 SAI1_TXD6 CPU.SAI1_TXD6 B3 NVCC_3V3 I/O internally used for BOOT config
J4.24 SAI1_TXD7 CPU.SAI1_TXD7 C1 NVCC_3V3 I/O internally used for BOOT config
J4.25 DGND DGND - - G

Pinout Table J5 pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
J5.1 DGND DGND - - G
J5.2 PCIE2_RXN CPU.PCIE2_RXN_N D24 - D
J5.3 PCIE2_RXP CPU.PCIE2_RXN_P D25 - D
J5.4 DGND DGND - - G
J5.5 PCIE2_TXN CPU.PCIE2_TXN_N E24 - D
J5.6 PCIE2_TXP CPU.PCIE2_TXN_P E25 - D
J5.7 DGND DGND - - G
J5.8 PCIE2_REF_CLKN CPU.PCIE2_REF_PAD_CLK_N F24 - D
J5.9 PCIE2_REF_CLKP CPU.PCIE2_REF_PAD_CLK_P F25 - D
J5.10 DGND DGND - - G
J5.11 CSI_P2_CKN CPU.MIPI_CSI2_CLK_N A19 - D
J5.12 CSI_P2_CKP CPU.MIPI_CSI2_CLK_P B19 - D
J5.13 DGND DGND - - G
J5.14 CSI_P2_DN0 CPU.MIPI_CSI2_D0_N C20 - D
J5.15 CSI_P2_DP0 CPU.MIPI_CSI2_D0_P D10 - D
J5.16 CSI_P2_DN1 CPU.MIPI_CSI2_D1_N A20 - D
J5.17 CSI_P2_DP1 CPU.MIPI_CSI2_D1_P B20 - D
J5.18 DGND DGND - - G
J5.19 CSI_P2_DN2 CPU.MIPI_CSI2_D2_N A21 - D
J5.20 CSI_P2_DP2 CPU.MIPI_CSI2_D2_P B21 - D
J5.21 CSI_P2_DN3 CPU.MIPI_CSI2_D3_N C19 - D
J5.22 CSI_P2_DP3 CPU.MIPI_CSI2_D3_P D19 - D
J5.23 DGND DGND - - G
J5.24 I2C4_SCL CPU.I2C4_SCL F8 NVCC_3V3 I/O
J5.25 I2C4_SDA CPU.I2C4_SDA F9 NVCC_3V3 I/O

Pinout Table JD5 pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage|domain Type Notes Alternative Functions
JD5.1 DGND DGND - - G
JD5.2 EEPROM_WP Internal EEPROM Write Protect - NVCC_3V3 I
JD5.3 NC Not Connected - - Z
JD5.4 JTAG_TCK CPU.JTAG_TCK T5 NVCC_3V3 I internal pull-up 10k to NVCC_3V3
JD5.5 JTAG_TMS CPU.JTAG_TMS V5 NVCC_3V3 I
JD5.6 JTAG_TDO CPU.JTAG_TDO U5 NVCC_3V3 O
JD5.7 JTAG_TDI CPU.JTAG_TDI W5 NVCC_3V3 I
JD5.8 JTAG_nTRST CPU.JTAG_TRST_B U6 NVCC_3V3 I
JD5.9 CPU_PORn CPU.POR_B

PMIC.RESETMCU

W20

3

NVCC_SNVS I/O internal pull-up 100k to NVCC_SNVS
JD5.10 NVCC_3V3 NVCC_3V3 - - S
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