Changes

|8 ||PS_SD0_DAT1||| - || -

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==== Ethernet GPIO - JP18 ====

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==== SPI,NAND - JP19 ====

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==== Digilent Pmod™ Compatible - JP23 ====

The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.

! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n

! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34

This configuration is in accordance with default routing of signals used for FMC connector.

====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)====

|+Bank #13 (HR)

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|+Bank #35 (HP)

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|+Bank #34 (HP)

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====Examples of valid combinations for Zynq 7015-based SOMs====

|+Bank #13 (HR)

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|+Bank #35 (HR)

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|+Bank #34 (HP)

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As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing.