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→SoC and SDRAM bank
===SoC and SDRAM bank===
The SoC model is i.MX8M QuadMX6Q:
<pre class="board-terminal">
armbian@sbcx:~/devel/stream/lmbench$ lscpu
{| class="wikitable"
|+
|-
!!!Mito8M!AxelLiteAxel Lite
|-
| rowspan="2" |SoC
|SoC
|NXP i.MX8M Quad|MX6Q
|-
|ARM frequency
[MHz]
|800 or 1300|996
|-
| rowspan="6" |SDRAM
|Type
|LPDDR4|DDR3
|-
|Frequency
[MHz]
|1600|533
|-
|Bus witdth
[bit]
|32|64
|-
|Theoretical bandwidth
[Gb/s]
|10268.4|2
|-
|Theoretical bandwidth
[GB/s]
|127.8|9
|-
|Size
[MB]
|3072|2048
|}
