Bureaucrats, dave_user, Administrators
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→SoC and SDRAM bank organization
====SoC and SDRAM bank organization====
armbian@Mito8M:~/devel/lmbench/tmp$ lscpu
Architecture: aarch64
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: ARM
Model: 4
Model name: Cortex-A53
Stepping: r0p4
CPU max MHz: 1300.0000
CPU min MHz: 800.0000
BogoMIPS: 16.66
L1d cache: unknown size
L1i cache: unknown size
L2 cache: unknown size
NUMA node0 CPU(s): 0-3
Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
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