a000298_approval, dave_user
551
edits
Changes
→Vivado design
[[File:An-belk-006-01.png|800px]]
===Bora + BoraEVB===
On BoraEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #34.
'''WARNING:''' due to a restraint introduced, from Vivado version 2017.1 onwards, the signal ETH1_TXCK can be routed only to a pad that is MRCC or SRCC input. As result from BELK 4.0.0 an hardware rework is needed on the BoraEVB board:
* Remove R183
* Remove R232
* Connect R183.2 with R232.1
This rework prevents the use of the PL SDRAM onboard of the BoraEVB (by default this ram is not mounted).
Here is the pinout assignment for the PHY1 on BoraEVB:
| ETH1_RXD3||IO_L7P_T1_34
|-
| ETH1_RXCK||<span style="text-decoration: line-through;">IO_L4N_T0_34</span> IO_L13P_T1_MRCC_34
|-
| ETH1_RXCTL||IO_L4P_T0_34
The project archive can be downloaded [https://www.dave.eu/system/files/area-riservata/AN-BELK-006-Enabling-dual-Gigabit.zip here].
===BoraLite + Adapter + BoraXEVB===On BoraXEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #13. The BoraLite Adapter take care of rerouting the ETH1_RXCK to meet the Vivado requirements. Here is the pinout assignment for the PHY1 on BoraXEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORAX SOM Signal'''|-| ETH1_TXD0||IO_L19P_T3_13|-| ETH1_TXD1||IO_L19N_T3_VREF_13|-| ETH1_TXD2||IO_L20P_T3_13|-| ETH1_TXD3||IO_L20N_T3_13|-| ETH1_TXCK||IO_L16P_T2_13|-| ETH1_TXCTL||IO_L16N_T2_13|-| ETH1_RXD0||IO_L17P_T2_13|-| ETH1_RXD1||IO_L17N_T2_13|-| ETH1_RXD2||IO_L18P_T2_13|-| ETH1_RXD3||IO_L18N_T2_13|-| ETH1_RXCK||IO_L14P_T2_SRCC_13|-| ETH1_RXCTL||IO_L15N_T2_DQS_13|-| ETH1_MDC||IO_L21N_T3_DQS_13|-| ETH1_MDIO||IO_L21P_T3_DQS_13|-|} I/O voltage of bank 13 must be set to 2.5V by configuring [[BoraXEVB#BANK13_VDDIO_selector_-_JP25|JP25 ]] as shown in the following table.{| class="wikitable" border="1"!Pins!Setting|-|1-2|closed|-|3-4|open|-|5-6|closed|-|7-8|open|-|9-10|open|-|11-12|open|-|} The project archive can be downloaded [https://www.dave.eu/system/files/area-riservata/AN-BELK-006-Enabling-dual-Gigabit.zip here] '''TODO''': add binaries ===Borax + BoraXEVB===
On BoraXEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #13.
'''WARNING:''' due to a restraint introduced, from Vivado version 2017.1 onwards, the signal ETH1_TXCK can be routed only to a pad that is MRCC or SRCC input. As result from BXELK 2.0.0 an hardware rework is needed on the BoraXEVB board:
* Remove RP84
* Remove R232
* Connect RP84.2 with R232.1
This rework prevents the use of the LVDS connector on BoraXEVB (J26).
Here is the pinout assignment for the PHY1 on BoraXEVB:
| ETH1_RXD3||IO_L18N_T2_13
|-
| ETH1_RXCK||<span style="text-decoration: line-through;">IO_L15P_T2_DQS_13</span> IO_L12P_T1_MRCC_13
|-
| ETH1_RXCTL||IO_L15N_T2_DQS_13
