__FORCETOC__ ==IntroductionConnectors and Pinout Table== === Connectors description ===In the following table are described all available connectors integrated on [[BORA Lite SOM]]:{| class="wikitable"|-!Connector name!Connector Type!Notes!Carrier board counterpart|-|J1|SODIMM DDR3 edge connector 204 pin||TE Connectivity 2-2013289-1|}The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA Lite pinout specifications. See the images below for reference: [[File:BORA_Lite-top-pin1-203.png|500px|thumb|BORA Lite TOP view|none]][[File:BORA_Lite-bottom-pin2-204.png|500px|thumb|BORA Lite BOTTOM view|none]] ===Pinout table naming conventions ===<section begin="Body" />
This chapter contains the pinout description of the BORA Lite SOM, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM BORA Lite connector.
Each row in the pinout tables contains the following information:
* {| class="wikitable" style="width:50%;"|-|'''Pin: reference '''| Reference to the connector pin* |-|'''Pin Name: pin ''' | Pin (signal) name on the Bora AxelLite connectors* |-|'''Internal <br>connections: connections ''' | Connections to the Bora components** CPU.<x> : pin connected to CPU (processing system) pad named <x>** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>** CAN.<x> : pin connected to the CAN transceiver** LAN.<x> : pin connected to the LAN PHY** USB.<x> : pin connected to the USB transceiver** NAND.<x>: pin connected to the flash NAND** NOR.<x>: pin connected to the flash NOR** SV.<x>: pin connected to voltage supervisor** MTR: pin connected to voltage monitors* |-|'''Ball/pin #: ''' | Component ball/pin number connected to signal* Supply Group: Power Supply Group|-|'''Voltage''' || I/O voltage levels |-* |'''Type''' | Pin type: pin type** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal* Voltage: I/O voltage levels|-|'''Notes'''|Remarks on special pin characteristics|-|}
|J1.41||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora Lite SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(BoraBoraLite)]].
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|J1.43||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.45||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.47||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.49||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.51||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.53||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.55||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.57||DGND||DGND||n.a.||||||||
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|J1.59||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.61||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.63||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.65||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
|-
|J1.67||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10|||||||| N.B. Although BANK 13 is not available on Bora Lite SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
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|J1.69||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.71||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9|||||||| Not available on Bora Lite SOMs equipped with the XC7Z007S/XC7Z010 SOC
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|J1.73||DGND||DGND||n.a.||||||||
|-|J1.75||ETH0_PHY_RST||LAN.RESET_N||41||||||||Internally connected to PS_MIO51_501
|J1.81||IO_25_34||FPGA.IO_25_34||T19||||||optionally ||Optionally connected to ETH PHY 25MHz OSC ENABLE<br>Optionally connected to USB 26MHz OSC ENABLE||
==J1 even SODIMM EVEN pins (2 to 204)declaration==
{| class="wikitable" {| {{table}}
|J1.2||DGND||DGND||n.a.||||||||
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|J2J1.4||3.3VIN||+3.3 V||n.a.||||||||
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|J2J1.6||3.3VIN||+3.3 V||n.a.||||||||
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|J2J1.8||3.3VIN||+3.3 V||n.a.||||||||
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|J2J1.10||3.3VIN||+3.3 V||n.a.||||||||
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|J1.12||DGND||DGND||n.a.||||||||
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|J1.14||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||||||Open-drain with internal pull-up (10K) to 3.3VINFor further details, please refer to [[Power (Bora/BoraLite)|Power Supply]]
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|J1.16||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||n.a.||||||||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply]]
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|J1.18||SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||||||For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
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|J1.20||MRSTN||MTR.MR||6||||||||Optionally internally connected to PORSTn (CPU.PS_POR_B_500)
For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]