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Created page with "{{InfoBoxTop}} {{Applies To BoraLite}} {{InfoBoxBottom}} ==Introduction== This chapter contains the pinout description of the BORA Lite SOM, grouped in two tables (odd and ev..."
{{InfoBoxTop}}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
==Introduction==
This chapter contains the pinout description of the BORA Lite SOM, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM BORA Lite connector.
Each row in the pinout tables contains the following information:
* Pin: reference to the connector pin
* Pin Name: pin (signal) name on the Bora connectors
* Internal connections: connections to the Bora components
** CPU.<x> : pin connected to CPU (processing system) pad named <x>
** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
** CAN.<x> : pin connected to the CAN transceiver
** LAN.<x> : pin connected to the LAN PHY
** USB.<x> : pin connected to the USB transceiver
** NAND.<x>: pin connected to the flash NAND
** NOR.<x>: pin connected to the flash NOR
** SV.<x>: pin connected to voltage supervisor
** MTR: pin connected to voltage monitors
* Ball/pin #: Component ball/pin number connected to signal
* Supply Group: Power Supply Group
* Type: pin type
** I = Input
** O = Output
** D = Differential
** Z = High impedance
** S = Power supply voltage
** G = Ground
** A = Analog signal
* Voltage: I/O voltage levels
==J1 odd pins (1 to 203)==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
| style="background:#f0f0f0;" align="center" |'''Type'''
| style="background:#f0f0f0;" align="center" |'''Voltage'''
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J1.1||DGND||DGND||n.a.||||||||
|-
|J1.13||ETH_LED1||LAN.LED1 / PME_N1||17||||||||
|-
|J1.15||ETH_LED2||LAN.LED2||15||||||||
|-
|J1.17||DGND||DGND||n.a.||||||||
|-
|J1.19||ETH_TXRX0_P||LAN.TXRXP_A||2||||||||
|-
|J1.21||ETH_TXRX0_M||LAN.TXRXM_A||3||||||||
|-
|J1.23||ETH_TXRX1_P||LAN.TXRXP_B||5||||||||
|-
|J1.25||ETH_TXRX1_M||LAN.TXRXM_B||6||||||||
|-
|J1.27||ETH_TXRX2_P||LAN.TXRXP_C||7||||||||
|-
|J1.29||ETH_TXRX2_M||LAN.TXRXM_C||8||||||||
|-
|J1.31||ETH_TXRX3_P||LAN.TXRXP_D||10||||||||
|-
|J1.33||ETH_TXRX3_M||LAN.TXRXM_D||11||||||||
|-
|J1.35||DGND||DGND||n.a.||||||||
|-
|J1.39||PS_MIO41_501||CPU.PS_MIO41_501||C17||||||||
|-
|J1.37||PS_MIO40_501||CPU.PS_MIO40_501||D14||||||||
|-
|J1.57||DGND||DGND||n.a.||||||||
|-
|J1.109||DGND||DGND||n.a.||||||||
|-
|J1.131||DGND||DGND||n.a.||||||||
|-
|J1.133||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||M19||||||||
|-
|J1.135||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||M20||||||||
|-
|J1.137||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||M18||||||||
|-
|J1.139||IO_L8P_T1_AD10P_35||FPGA.IO_L8P_T1_AD10P_35||M17||||||||
|-
|J1.141||IO_L11N_T1_SRCC_35||FPGA.IO_L11N_T1_SRCC_35||L17||||||||
|-
|J1.173||IO_L12P_T1_MRCC_35||FPGA.IO_L12P_T1_MRCC_35||K17||||||||
|-
|J1.143||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||L16||||||||
|-
|J1.145||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||K19||||||||
|-
|J1.147||IO_L10N_T1_AD11N_35||FPGA.IO_L10N_T1_AD11N_35||J19||||||||
|-
|J1.149||IO_L14P_T2_AD4P_SRCC_35||FPGA.IO_L14P_T2_AD4P_SRCC_35||J18||||||||
|-
|J1.151||IO_L14N_T2_AD4N_SRCC_35||FPGA.IO_L14N_T2_AD4N_SRCC_35||H18||||||||
|-
|J1.153||DGND||DGND||n.a.||||||||
|-
|J1.155||IO_0_35||FPGA.IO_0_35||G14||||||||
|-
|J1.157||IO_25_35||FPGA.IO_25_35||J15||||||||
|-
|J1.159||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||L19||||||||
|-
|J1.161||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||L20||||||||
|-
|J1.163||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||J20||||||||
|-
|J1.165||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||H20||||||||
|-
|J1.167||IO_L21P_T3_DQS_AD14P_35||FPGA.IO_L21P_T3_DQS_AD14P_35||N15||||||||
|-
|J1.169||IO_L21N_T3_DQS_AD14N_35||FPGA.IO_L21N_T3_DQS_AD14N_35||N16||||||||
|-
|J1.171||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||K18||||||||
|-
|J1.175||DGND||DGND||n.a.||||||||
|-
|J1.177||IO_L6N_T0_VREF_35||FPGA.IO_L6N_T0_VREF_35||F17||||||||
|-
|J1.179||IO_L6P_T0_35||FPGA.IO_L6P_T0_35||F16||||||||
|-
|J1.181||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||G15||||||||
|-
|J1.183||IO_L19P_T3_35||FPGA.IO_L19P_T3_35||H15||||||||
|-
|J1.185||IO_L3P_T0_DQS_AD1P_35||FPGA.IO_L3P_T0_DQS_AD1P_35||E17||||||||
|-
|J1.187||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D18||||||||
|-
|J1.189||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||H16||||||||
|-
|J1.191||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||H17||||||||
|-
|J1.193||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||B20||||||||
|-
|J1.195||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||C20||||||||
|-
|J1.197||IO_L2P_T0_AD8P_35||FPGA.IO_L2P_T0_AD8P_35||B19||||||||
|-
|J1.199||IO_L2N_T0_AD8N_35||FPGA.IO_L2N_T0_AD8N_35||A20||||||||
|-
|J1.201||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|-
|}
==J1 even pins (2 to 204)==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
| style="background:#f0f0f0;" align="center" |'''Type'''
| style="background:#f0f0f0;" align="center" |'''Voltage'''
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J1.2||DGND||DGND||n.a.||||||||
|-
|J2.4||3.3VIN||+3.3 V||n.a.||||||||
|-
|J2.6||3.3VIN||+3.3 V||n.a.||||||||
|-
|J2.8||3.3VIN||+3.3 V||n.a.||||||||
|-
|J2.10||3.3VIN||+3.3 V||n.a.||||||||
|-
|J1.12||DGND||DGND||n.a.||||||||
|-
|J2.22||VBAT_BKP||RTC.VBAT||6||||||||
|-
|J1.24||PS_MIO49_501||CPU.PS_MIO49_501||C12||||||||
|-
|J1.26||PS_MIO48_501||CPU.PS_MIO48_501||B12||||||||
|-
|J1.28||PS_MIO47_501||CPU.PS_MIO47_501||B14||||||||
|-
|J1.30||DGND||DGND||n.a.||||||||
|-
|J1.32||PS_MIO46_501||CPU.PS_MIO46_501||D16||||||||
|-
|J1.34||PS_MIO45_501 ||CPU.PS_MIO45_501||B15||||||||
|-
|J1.36||PS_MIO44_501||CPU.PS_MIO44_501||F13||||||||
|-
|J1.38||PS_MIO43_501||CPU.PS_MIO43_501||A9||||||||
|-
|J1.40||PS_MIO42_501||CPU.PS_MIO42_501||E12||||||||
|-
|J1.42||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||C8<br>1||||||||See also [[Watchdog_(BoraLite)|this page]]
|-
|J1.46||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.48||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.50||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.52||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.54||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J3.58||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.60||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J1.56||DGND||DGND||n.a.||||||||
|-
|J1.122||DGND||DGND||n.a.||||||||
|-
|J1.146||DGND||DGND||n.a.||||||||
|-
|J1.148||IO_L18P_T2_AD13P_35||FPGA.IO_L18P_T2_AD13P_35||G19||||||||
|-
|J1.150||IO_L18N_T2_AD13N_35||FPGA.IO_L18N_T2_AD13N_35||G20||||||||
|-
|J1.152||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||F20||||||||
|-
|J1.154||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||F19||||||||
|-
|J1.156||IO_L22N_T3_AD7N_35||FPGA.IO_L22N_T3_AD7N_35||L15||||||||
|-
|J1.158||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||L14||||||||
|-
|J1.160||IO_L20P_T3_AD6P_35||FPGA.IO_L20P_T3_AD6P_35||K14||||||||
|-
|J1.162||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||J14||||||||
|-
|J1.164||DGND||DGND||n.a.||||||||
|-
|J1.166||IO_L23N_T3_35||FPGA.IO_L23N_T3_35||M15||||||||
|-
|J1.168||IO_L23P_T3_35||FPGA.IO_L23P_T3_35||M14||||||||
|-
|J1.170||IO_L24P_T3_AD15P_35||FPGA.IO_L24P_T3_AD15P_35||K16||||||||
|-
|J1.172||IO_L24N_T3_AD15N_35||FPGA.IO_L24N_T3_AD15N_35||J16||||||||
|-
|J1.174||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||E18||||||||
|-
|J1.176||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E19||||||||
|-
|J1.178||IO_L16N_T2_35||FPGA.IO_L16N_T2_35||G18||||||||
|-
|J1.180||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||G17||||||||
|-
|J1.182||IO_L4P_T0_35||FPGA.IO_L4P_T0_35||D19||||||||
|-
|J1.184||IO_L4N_T0_35||FPGA.IO_L4N_T0_35||D20||||||||
|-
|J1.186||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|-
|J1.188||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|-
|J1.192||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|-
|J1.190||DGND||DGND||n.a.||||||||
|-
|J1.194||USBOTG_CPEN||USB.CPEN||7||||||||
|-
|J1.196||OTG_VBUS||USB.OTG_VBUS||2||||||||
|-
|J1.198||OTG_ID||USB.ID||1||||||||
|-
|J1.200||USBP1||USB.DP||6||||||||
|-
|J1.202||USBM1||USB.DM||5||||||||
|-
|J1.204||DGND||DGND||n.a.||||||||
|-
|}
{{Applies To BoraLite}}
{{InfoBoxBottom}}
==Introduction==
This chapter contains the pinout description of the BORA Lite SOM, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM BORA Lite connector.
Each row in the pinout tables contains the following information:
* Pin: reference to the connector pin
* Pin Name: pin (signal) name on the Bora connectors
* Internal connections: connections to the Bora components
** CPU.<x> : pin connected to CPU (processing system) pad named <x>
** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>
** CAN.<x> : pin connected to the CAN transceiver
** LAN.<x> : pin connected to the LAN PHY
** USB.<x> : pin connected to the USB transceiver
** NAND.<x>: pin connected to the flash NAND
** NOR.<x>: pin connected to the flash NOR
** SV.<x>: pin connected to voltage supervisor
** MTR: pin connected to voltage monitors
* Ball/pin #: Component ball/pin number connected to signal
* Supply Group: Power Supply Group
* Type: pin type
** I = Input
** O = Output
** D = Differential
** Z = High impedance
** S = Power supply voltage
** G = Ground
** A = Analog signal
* Voltage: I/O voltage levels
==J1 odd pins (1 to 203)==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
| style="background:#f0f0f0;" align="center" |'''Type'''
| style="background:#f0f0f0;" align="center" |'''Voltage'''
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J1.1||DGND||DGND||n.a.||||||||
|-
|J1.13||ETH_LED1||LAN.LED1 / PME_N1||17||||||||
|-
|J1.15||ETH_LED2||LAN.LED2||15||||||||
|-
|J1.17||DGND||DGND||n.a.||||||||
|-
|J1.19||ETH_TXRX0_P||LAN.TXRXP_A||2||||||||
|-
|J1.21||ETH_TXRX0_M||LAN.TXRXM_A||3||||||||
|-
|J1.23||ETH_TXRX1_P||LAN.TXRXP_B||5||||||||
|-
|J1.25||ETH_TXRX1_M||LAN.TXRXM_B||6||||||||
|-
|J1.27||ETH_TXRX2_P||LAN.TXRXP_C||7||||||||
|-
|J1.29||ETH_TXRX2_M||LAN.TXRXM_C||8||||||||
|-
|J1.31||ETH_TXRX3_P||LAN.TXRXP_D||10||||||||
|-
|J1.33||ETH_TXRX3_M||LAN.TXRXM_D||11||||||||
|-
|J1.35||DGND||DGND||n.a.||||||||
|-
|J1.39||PS_MIO41_501||CPU.PS_MIO41_501||C17||||||||
|-
|J1.37||PS_MIO40_501||CPU.PS_MIO40_501||D14||||||||
|-
|J1.57||DGND||DGND||n.a.||||||||
|-
|J1.109||DGND||DGND||n.a.||||||||
|-
|J1.131||DGND||DGND||n.a.||||||||
|-
|J1.133||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||M19||||||||
|-
|J1.135||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||M20||||||||
|-
|J1.137||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||M18||||||||
|-
|J1.139||IO_L8P_T1_AD10P_35||FPGA.IO_L8P_T1_AD10P_35||M17||||||||
|-
|J1.141||IO_L11N_T1_SRCC_35||FPGA.IO_L11N_T1_SRCC_35||L17||||||||
|-
|J1.173||IO_L12P_T1_MRCC_35||FPGA.IO_L12P_T1_MRCC_35||K17||||||||
|-
|J1.143||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||L16||||||||
|-
|J1.145||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||K19||||||||
|-
|J1.147||IO_L10N_T1_AD11N_35||FPGA.IO_L10N_T1_AD11N_35||J19||||||||
|-
|J1.149||IO_L14P_T2_AD4P_SRCC_35||FPGA.IO_L14P_T2_AD4P_SRCC_35||J18||||||||
|-
|J1.151||IO_L14N_T2_AD4N_SRCC_35||FPGA.IO_L14N_T2_AD4N_SRCC_35||H18||||||||
|-
|J1.153||DGND||DGND||n.a.||||||||
|-
|J1.155||IO_0_35||FPGA.IO_0_35||G14||||||||
|-
|J1.157||IO_25_35||FPGA.IO_25_35||J15||||||||
|-
|J1.159||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||L19||||||||
|-
|J1.161||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||L20||||||||
|-
|J1.163||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||J20||||||||
|-
|J1.165||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||H20||||||||
|-
|J1.167||IO_L21P_T3_DQS_AD14P_35||FPGA.IO_L21P_T3_DQS_AD14P_35||N15||||||||
|-
|J1.169||IO_L21N_T3_DQS_AD14N_35||FPGA.IO_L21N_T3_DQS_AD14N_35||N16||||||||
|-
|J1.171||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||K18||||||||
|-
|J1.175||DGND||DGND||n.a.||||||||
|-
|J1.177||IO_L6N_T0_VREF_35||FPGA.IO_L6N_T0_VREF_35||F17||||||||
|-
|J1.179||IO_L6P_T0_35||FPGA.IO_L6P_T0_35||F16||||||||
|-
|J1.181||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||G15||||||||
|-
|J1.183||IO_L19P_T3_35||FPGA.IO_L19P_T3_35||H15||||||||
|-
|J1.185||IO_L3P_T0_DQS_AD1P_35||FPGA.IO_L3P_T0_DQS_AD1P_35||E17||||||||
|-
|J1.187||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D18||||||||
|-
|J1.189||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||H16||||||||
|-
|J1.191||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||H17||||||||
|-
|J1.193||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||B20||||||||
|-
|J1.195||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||C20||||||||
|-
|J1.197||IO_L2P_T0_AD8P_35||FPGA.IO_L2P_T0_AD8P_35||B19||||||||
|-
|J1.199||IO_L2N_T0_AD8N_35||FPGA.IO_L2N_T0_AD8N_35||A20||||||||
|-
|J1.201||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|-
|}
==J1 even pins (2 to 204)==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
| style="background:#f0f0f0;" align="center" |'''Type'''
| style="background:#f0f0f0;" align="center" |'''Voltage'''
| style="background:#f0f0f0;" align="center" |'''Note'''
|-
|J1.2||DGND||DGND||n.a.||||||||
|-
|J2.4||3.3VIN||+3.3 V||n.a.||||||||
|-
|J2.6||3.3VIN||+3.3 V||n.a.||||||||
|-
|J2.8||3.3VIN||+3.3 V||n.a.||||||||
|-
|J2.10||3.3VIN||+3.3 V||n.a.||||||||
|-
|J1.12||DGND||DGND||n.a.||||||||
|-
|J2.22||VBAT_BKP||RTC.VBAT||6||||||||
|-
|J1.24||PS_MIO49_501||CPU.PS_MIO49_501||C12||||||||
|-
|J1.26||PS_MIO48_501||CPU.PS_MIO48_501||B12||||||||
|-
|J1.28||PS_MIO47_501||CPU.PS_MIO47_501||B14||||||||
|-
|J1.30||DGND||DGND||n.a.||||||||
|-
|J1.32||PS_MIO46_501||CPU.PS_MIO46_501||D16||||||||
|-
|J1.34||PS_MIO45_501 ||CPU.PS_MIO45_501||B15||||||||
|-
|J1.36||PS_MIO44_501||CPU.PS_MIO44_501||F13||||||||
|-
|J1.38||PS_MIO43_501||CPU.PS_MIO43_501||A9||||||||
|-
|J1.40||PS_MIO42_501||CPU.PS_MIO42_501||E12||||||||
|-
|J1.42||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||C8<br>1||||||||See also [[Watchdog_(BoraLite)|this page]]
|-
|J1.46||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.48||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.50||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.52||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J1.54||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
|J3.58||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J3.60||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9|||||||| Not available on Bora SOMs equipped with the XC7Z010 SOC
|-
|J1.56||DGND||DGND||n.a.||||||||
|-
|J1.122||DGND||DGND||n.a.||||||||
|-
|J1.146||DGND||DGND||n.a.||||||||
|-
|J1.148||IO_L18P_T2_AD13P_35||FPGA.IO_L18P_T2_AD13P_35||G19||||||||
|-
|J1.150||IO_L18N_T2_AD13N_35||FPGA.IO_L18N_T2_AD13N_35||G20||||||||
|-
|J1.152||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||F20||||||||
|-
|J1.154||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||F19||||||||
|-
|J1.156||IO_L22N_T3_AD7N_35||FPGA.IO_L22N_T3_AD7N_35||L15||||||||
|-
|J1.158||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||L14||||||||
|-
|J1.160||IO_L20P_T3_AD6P_35||FPGA.IO_L20P_T3_AD6P_35||K14||||||||
|-
|J1.162||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||J14||||||||
|-
|J1.164||DGND||DGND||n.a.||||||||
|-
|J1.166||IO_L23N_T3_35||FPGA.IO_L23N_T3_35||M15||||||||
|-
|J1.168||IO_L23P_T3_35||FPGA.IO_L23P_T3_35||M14||||||||
|-
|J1.170||IO_L24P_T3_AD15P_35||FPGA.IO_L24P_T3_AD15P_35||K16||||||||
|-
|J1.172||IO_L24N_T3_AD15N_35||FPGA.IO_L24N_T3_AD15N_35||J16||||||||
|-
|J1.174||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||E18||||||||
|-
|J1.176||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E19||||||||
|-
|J1.178||IO_L16N_T2_35||FPGA.IO_L16N_T2_35||G18||||||||
|-
|J1.180||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||G17||||||||
|-
|J1.182||IO_L4P_T0_35||FPGA.IO_L4P_T0_35||D19||||||||
|-
|J1.184||IO_L4N_T0_35||FPGA.IO_L4N_T0_35||D20||||||||
|-
|J1.186||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|-
|J1.188||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|-
|J1.192||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
|-
|J1.190||DGND||DGND||n.a.||||||||
|-
|J1.194||USBOTG_CPEN||USB.CPEN||7||||||||
|-
|J1.196||OTG_VBUS||USB.OTG_VBUS||2||||||||
|-
|J1.198||OTG_ID||USB.ID||1||||||||
|-
|J1.200||USBP1||USB.DP||6||||||||
|-
|J1.202||USBM1||USB.DM||5||||||||
|-
|J1.204||DGND||DGND||n.a.||||||||
|-
|}
