| Linux kernel [[BELK-AN-008:_Programming_the_FPGA_Bitstream_with_U-Boot|FPGA Bitstream]] || [[mirror:bora/belk-4.01.0/belk-4.01.0_bora_BASE_fpga.0_uImagebit|uImagefpga.bit]] || [[mirror:bora/belk-4.01.0/belk-4.01.0_borax_BASE__fpga.0_uImagebit|uImagefpga.bit]]
|-
| Device tree Linux kernel || [[mirror:bora/belk-4.01.0/belk-4.01.0_bora.dtb0_uImage|bora.dtbuImage]] || [[mirror:bora/belk-4.01.0/belk-4.01.0_bora.dtb0_uImage|bora.dtbuImage]]
|-
| Device tree || [[mirror:bora/belk-4.1.0/belk-4.1.0_bora.dtb|bora.dtb]] || [[mirror:bora/belk-4.1.0/belk-4.1.0_bora.dtb|bora.dtb]]|-|Root File System || [[mirror:bora/belk-4.01.0/belk-4.01.0_bora0_dave-image-devel-bora.tar.gzbz2|bora.tar.gzbz2]] || [[mirror:bora/belk-4.01.0/belk-4.01.0_bora0_dave-image-devel-bora.tar.gzbz2|bora.tar.gzbz2]]
|}
== Release notes ==
=== BELK 4.1.0 ===
Updates:
# Added support for [https://www.dave.eu/products/som/xilinx/zynq-XC7Z010-XC7Z020_boralite BoraLite SOM]
==== Known Limitations ====
{| class="wikitable"
|-
!ID
!Component
!Subsystem
!Description
|-
|0001
|BoraEVB
|External DDR3 bank (BoraEVB only)
|DDR3 bank can be populated on request. For more details please refer to [mailto:sales@dave.eu Sales Department].
|-
|0002
|BoraEVB/BoraXEVB
|ETH1 interface
|Please refer to [[AN-BELK-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB/BoraXEVB|this application note]] for second Ethernet interface support.
|-
|0003
|BoraEVB/BoraXEVB
|RTC
|Date/time retention is limited to about 4 hours.
|-
|0004
|BoraEVB/BoraXEVB
|System clock runs slower
|As per [https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841831/CPU+frequency+scaling#Missing%20Features,%20Known%20Issues%20and%20Limitations Xilinx issue], @333MHz (speedgrade -3) system clock is slower then expected
|}
=== BELK 4.0.0 / BXELK 2.0.0 ===
<code>export CC=gcc</code>
|-
|0007
|BoraEVB/BoraXEVB
|System clock runs slower
|As per [https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841831/CPU+frequency+scaling#Missing%20Features,%20Known%20Issues%20and%20Limitations Xilinx issue], @333MHz (speedgrade -3) system clock is slower then expected
|-
|}
{| class="wikitable"
|-
|-
!ID
!Component
!Issue
!Description
|-
|0001
|BoraEVB
|External DDR3 bank (BoraEVB only)
|DDR3 bank can be populated on request. For more details please refer to [mailto:sales@dave.eu Sales Department].
|-
|0002
|BoraEVB/BoraXEVB
|ETH1 interface
|Please refer to [[AN-BELK-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB/BoraXEVB|this application note]] for second Ethernet interface support.
|-
|0003
|BoraEVB/BoraXEVB
|RTC
|Date/time retention is limited to about 4 hours.
|}
=== BELK/BXELK older releases === For BELK/BXELK older releases information, please click on Expand here below (on the right) <div class="mw-collapsible mw-collapsed"> ==== BELK 3.0.1 / BXELK 1.0.0 ====
Updates: added support for BoraX/BoraXEVB evaluation system
(BoraXEVB only) For LCD interfacing, please refer to [[AN-BELK-004:_Interfacing_BoraEVB/BoraXEVB_to_TFT_LCD_display|this application note]].
===== Known Limitations =====
{| class="wikitable"
|}
==== BELK 3.0.0 ====
Updates:
(BoraXEVB only) For LCD interfacing, please refer to [[AN-BELK-004:_Interfacing_BoraEVB/BoraXEVB_to_TFT_LCD_display|this application note]].
===== Known Limitations =====
{| class="wikitable"
|}
==== BELK 2.2.0 ====
Updates:
# Updated U-Boot and Linux versions
===== Known Limitations =====
{| class="wikitable"
|}
==== BELK 2.1.0 ====
Updates:
# First [[Advanced_use_of_Yocto_build_system_(BELK/BXELK)|Yocto Daisy (1.6) BSP Release]]
===== Known Limitations =====
{| class="wikitable"
|}
==== BELK 2.0.0 ====
Updates:
# Updated supported drivers list (please refer to [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components | BELK_software_components]])
===== Known Limitations =====
The following table reports the known limitations of this BELK release: