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→Creating and Running a New Custom Overlay: Approach #1
====Creating and Running a New Custom Overlay: Approach #1====
We created a custom overlay associated with the hardware implementation of the FIR filter. This first approach made use of the FIR Compiler tool provided by Vivado.
The fundamental steps required to do this are:
*Opening a new Vivado project, selecting ''RTL project'' and ''Bora SOM'' as the target board
*Creating your block design
**Adding ''FIR compiler'' block (included in Vivado default IP) and setting it up
**Adding ''AXI direct memory access'' block and setting it up
**On ''ZYNQ7 Processing System'' block, enabling a ''High-Performance AXI 32b/64b Slave Ports'' on interface HP0
**Connecting AXIS_DATA bus of AXI and FIR block
**''Runnin Connection Automation'' to complete wiring
*Creating Hierarchy of AXI and FIR block named <code>filter</code>
*Exporting bitstream file running ''Generate Bitstream''
*Exporting block design using Tcl console command <code>write_bd_tcl </path/name>.tcl</code>
*Renaming generated files as <code>overlay_name>.bit</code> and <code><overlay_name>.tcl</code>
*Creating a folder named <code><overlay_name></code> and inserting generated files
*Copying the folder to the target's filesystem in <code>pynq/overlays/</code> direcrtory.
=====Running Custom Overlays with Generic Driver =====
=====Running Custom Overlays with IP-Specific Driver =====
To access the overlay with a specific driver:*Import <code>DefaultHierarchy</code> from <code>pynq</code>* sezione da approfondire e riscrivere meglio */create a new class for FIR filter with a method to communicate directly thorough a DMA buffer/* da testare exportazione con diversi setaggi da vivado per create a <code>checkhierarchy *</code> method to check the IP contained under ''filter'' hierarchy
====Creating and Running a New Custom Overlay: Approach #2====