===Implementing a Hardware-Accelerated Version of the FIR Filter in PL===
To accelerate a access an hardware-accelerated function from Python function on the Zynq-7000, PYNQ can requires to load a custom overlay.Overlays are built with Vivado 2018.2 and are composed by: - fpga *an FPGA bitstream (*.bit file) - *a block design (*.tcl file)
The test consisted of the following steps: