Changes

==Introduction==To understand the structure of [[Bora Embedded Linux Kit (BELK)]], it is necessary These kits introduce some significant differences with respect to describe the basic organization of Xilinx Vivado Design Suite/Xilinx SDK and to recall briefly the recent history of development tools provided by Xilinxprevious versions.The characterizing items are: ==A little bit of history==At the time of this writing (October 2013) Xilinx *FSBL is migrating from mature ISE 14.x Design Suite - that should be no longer used as the last series of this suite first- to the new Vivado environmentstage bootloader. Both are composed It is replaced by several programs and some of these are in commonU-Boot SPL. From *Yocto build system is fully integrated into the general standpoint, the main difference between ISE kit and Vivado - even if ISE does support Zynq - it is that the latter has been expressively conceived used to support newer SoC architectures such as Zynq, besides traditional FPGAs. Thus, adopting Vivado as build all the default environment for BELK/BXELK would seem software running on the natural choicetarget. HoweverConsequently, the migration process mentioned above has just begun and the majority of application notes and reference designs released by Xilinx still refers to ISE suite. Plus Vivado SDK tool chain is still a little bit "green" and several bug fixes and improvements are introduced by every new releaseno longer used. Since Bora was presented in 2013 and because this product addresses long longevity markets such as industrial and biomedical*To simplify the installation of host-side tools, a [[Managed Virtual Machine (MVM)]] is provided, '''DAVE Embedded Systems''' chose to build BELK/BXELK upon Vivado that undoubtedly represents today containing all the future of Xilinx development environmentsrequired tools. 

 The typical linuxLinux-based Zynq design is composed of the following parts:* FSBL (or U-boot SPL for BELK(first-4.0.0 or newer and BXELK-2.0.0 or newerstage bootloader)* U-Boot(second-stage bootloader)

Generally speaking, these parts - (in the binary/sinthesized synthesized form - ) are combined together in one monolithic file that is stored in a non-volatile memory such as SPI NOR flash. Generating this file is quite easy as described by Vivado documentation. However , in real world products, this may be too rigid because developers may want to handle these parts separately and independently.Starting from BELK-4.0.0 and BXELK-2.0.0 developers can take advantages of Thanks to the flexibility use of U-boot Boot dual stage bootloader support that allows to handle all binaries , these binary files can be handled separately and independently instead of a unique monolithic file. FSBL creation through Vivado SDK environment is no longer needed. U-boot SPL bootloader is now responsible to correctly initialize the PS (Processing System) based on configurations from the Vivado project.

The ambitious objective is to provide a complete, user -friendly, integrated environment that allows software developers to deal with FPGA development even if they are not familiar with this technology, by hiding a lot of its complexities [2]. As usual , this ease of use comes at the expence expense of control and flexibility. This could not be acceptable in many cases where engineers need to control and customize many aspects of the project to implement what is required by system specifications. For this reason, BELK and BXELK have been built around Vivado but some deviations from the default development approach suggested by Xilinx have been introduced, in order to '''push the modularization and the maintainability of the projects to the maximum possible extent'''.