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→Basic structure of Vivado Design Suite and integration into BELK/BXELK
Generally speaking, these parts - in the binary/synthesized form - are combined together in one monolithic file that is stored in a non-volatile memory such as SPI NOR flash. Generating this file is quite easy as described by Vivado documentation. However, in real world products, this may be too rigid because developers may want to handle these parts separately and independently.
==Basic structure of Vivado Design Suite and integration into BELK/BXELK==
Vivado/SDK [1] can be viewed as a collection of programs required to deal with all of the development aspects related to Xilinx components (software running on ARM cores, FPGA fabric verification and programming, power estimation etc.). These include strictly FPGA-related tools such as Floorplanner and pure-software development tools such as SDK.
The ambitious objective is to provide a complete, user -friendly, integrated environment that allows software developers to deal with FPGA development even if they are not familiar with this technology, by hiding a lot of its complexities [2]. As usual this ease of use comes at the expence expense of control and flexibility. This could not be acceptable in many cases where engineers need to control and customize many aspects of the project to implement what is required by system specifications. For this reason, BELK and BXELK have been built around Vivado but some deviations from the default development approach suggested by Xilinx have been introduced, in order to '''push the modularization and the maintainability of the projects to the maximum possible extent'''.
The following pictures show respectively the Vivado/SDK default development flow and how this has been integrated in into the BELK/BXELK infrastructure.
[[File:Belk-vivado-sdk-development-flow.png|thumbnail|center|300px|Vivado/SDK development flow (BELK <= 3.0.2 and BXELK <= 1.0.1)]]
[[File:Belk-vivado-sdk-integration.png|thumbnail|center|300px|Vivado/SDK integration into BELK/BXELK]]
