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→Structure of BELK/BXELK reference designs
The typical linux-based Zynq design is composed by the following parts:
* FSBL(or U-boot SPL for BELK-4.0.0 / BXELK-2.0.0)
* U-Boot
* device tree file
Generally speaking, these parts - in the binary/sinthesized form - are combined together in one monolithic file that is stored in a non-volatile memory such as SPI NOR flash. Generating this file is quite easy as described by Vivado documentation. However in real world products, this may be too rigid because developers may want to handle these parts separately and independently.
Starting from BELK-4.0.0 and BXELK-2.0.0 developers can take advantages of the flexibility of U-boot dual stage bootloader support that allows to handle all binaries separately and independently instead of a unique monolithic file. FSBL creation through Vivado SDK environment is no longer needed. U-boot SPL bootloader is now responsible to correctly initialize the PS (Processing System) based on configurations from the Vivado project.
==Basic structure of Vivado Design Suite and integration into BELK/BXELK==
