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{{AppliesToNaon}}
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===IntroductionOverview===
DM8148 processor provides a rich video subsystem that integrates video ports. These are described in detail on chapter 12 of [http://www.ti.com/litv/pdf/sprugz8a| Technical Reference Manual].
There are three video inputs:* VIN0* VIN1* camera parallel interface (CPI).From the architectural standpoint these VIN0 and VIN1 ports belong to the HDVPSS subsytems. For the sake of completeness a simplified block diagram of HDVPSS is shown below.
[[File:Dm8148-hdvpss-bd.png|thumbnail|center]]
Camera parallel interface belongs to the Imaging Subsystem (ISS). As ISS documentation is released under NDA, no informations are provided here. For more details about it please contact your local Texas Instruments sales representative or FAE.
===Routing on Naon connectors===
The following tables summirizes which signals are routed to Naon connectors and thus are available to user application.
{| {{table border="1"}}
| align="center" style="background:#f0f0f0;"|'''Processor pad'''
