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AMP can be implemented on homogeneous [1] and heterogeneous architectures. Either way, it poses significant challenges when it comes to handle resources that are unavoidably shared across different cores. ARM cores integrates TrustZone technology that can be exploited to face such issues, as described for example in [[BRX-WP001:_Real-timeness,_system_integrity_and_TrustZone®_technology_on_AMP_configuration|this document]].
Other system-on-chips (SOC) implements proprietary solution to handle the access to the shared resources. [http://www.nxp.com/pages/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX NXP i.MX6SoloX] is an example of such components, as it integrates a so called ''Resource Domain Controller'' (RDC), that " provides robust support for the isolation of destination memory mapped locations such as peripherals and memory to a single core, a bus master, or set of cores and bus masters" as stated by the manufacturer [2].
This white paper describes an i.MX6UL-based AMP solution that has been implemented for a custom product.
[[File:TBDSoloX-AMP.png|thumb|center|600px|captionSimplified block diagram of the AMP configuration]]
Is this case the role of the GPOS is played by Linux, while FreeRTOS has been used as real-time operating system [1].
For this specific application, it is required that the M4 core has exclusive access of to the following resources:
*GPT (General Purpose Timer), including associated I/Os
*some additional GPIOs.
Satisfying the first requirement has been the trickiest challenge because, by default, U-Boot and Linux kernel make use of GPT timer, as per official BSP released by NXP. This is not a big deal for U-Boot, because it just uses this timer to handle timeouts and to measure time intervals. The things are more complicated with regard to the Linux kernel, because GPT is used as clock source. As such, it is involved in the scheduling process and it is dynamically reconfigured over the time, depending on power saving policies.
To solve this issue, both U-Boot and Linux kernel have been modified, in order to use EPIT timer instead. In spite of this modification, we have been able to preserve power saving strategiesmechanisms.
In order to protect the peripherals that have to be under the exclusive control of the M4 core, RDC has been configured properlyaccordingly. For example, the memory area in which GPT registers are mapped, is accessible by the M4 core only. RDC initialization is performed by M4 itself. It is worth remembering that the its granularity is an important factor that has to be taken in consideration. In this application, for example, it has had to use choose different GPIO banksfor M4 and A9. In case the same bank was chosen, it would have been impossible to partition GPIOs across the two cores, because some resources are shared among all of the GPIOs belonging to the same bank (for example the clocks feeding the functional block). For this reason, two different banks have been chosen.
About boot requirements, U-Boot has been configured in order to get the following bootstrap sequence:
