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MISC-TN-003: Asymmetric multiprocessing on NXP i.MX6SoloX

1,898 bytes added, 08:23, 13 January 2017
Implementation
[2] See NXP i.MX 6SoloX Applications Processor Reference Manual (IMX6SXRM).
==Implementation==
The following image shows in more detail the implementation a simplified block diagram of the implemented solution.
Is this case the role of the GPOS is played by Linux, while FreeRTOS has been used as real-time operating system [1].
In For this specific application, it is required that the M4 core has exclusive access of the following resources:*GPT (General Purpose Timer), including associated I/Os*some additional GPIOs belonging to the bank GPIO2.It is also required that M4 firmware is booted before the Linux kerneland that the Linux kernel has exclusive control of some other GPIOS.  Satisfying the first requirement has been the trickiest challenge because, by default, U-Boot and Linux kernel make use of GPT timer, as per official BSP released by NXP. This is not a big deal for U-Boot, because it just uses this timer to handle timeouts and to measure time intervals. The things are more complicated with regard to the Linux kernel, because GPT is used as clock source. As such, it is involved in the scheduling process and it is dynamically reconfigured over the time, depending on power saving policies. To solve this issue, both U-Boot and Linux kernel have been modified, in order to use EPIT timer instead. In spite of this modification, we have been able to preserve power saving strategies. In order to protect the peripherals that have to be under the exclusive control of the M4 core, RDC has been configured properly. For example, the memory area in which GPT registers are mapped, is accessible by the M4 core only. RDC initialization is performed by M4 itself. It is worth remembering that the granularity is an important factor that has to be taken in consideration. In this application, for example, it has had to use different GPIO banks About boot requirements, U-Boot has been configured in order to get the following bootstrap sequence:#A9 core #*comes out of reset#*executes bootrom#*perform basic hardware initializations#*fetches U-Boot bootloader from flash memory and copies it in SDRAM#*executes U-Boot from SDRAM#in turn, U-Boot#*fetches M4 firmware from flash#*starts M4 core#*fetches Linux kernel and DTB from flash and copies them in SDRAM#*starts Linux kernel on Cortex-A9 core.#once Linux kernel has completed the bootstrap process, a user space application establishes a communication channel with M4 core, through [https://www.kernel.org/doc/Documentation/remoteproc.txt RPMsg]. 
To satisfy the first requirement, a
[1] For more details please refer to the [http://www.nxp.com/pages/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX?tab=Design_Tools_Tab FreeRTOS™ BSP for the i.MX 6SoloX ARM® Cortex®-M4 core].
 
==Conclusion==
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