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==A little bit of history==
At the time of this writing (October 2013) Xilinx is migrating from mature ISE 14.x Design Suite - that should be the last series of this suite - to the new Vivado environment. Both are composed by several programs and some of these are in common. From the general standpoint, the main difference between ISE and Vivado - even if ISE does support Zynq - is that the latter has been expressively conceived to support newer SoC architectures such as Zynq, besides traditional FPGAs. Thus, adopting Vivado as the default environment for BELK /BXELK would seem the natural choice. However, the migration process mentioned above has just begun and the majority of application notes and reference designs released by Xilinx still refers to ISE suite. Plus Vivado is still a little bit "green" and several bug fixes and improvements are introduced by every new release.
Since Bora was presented in 2013 and because this product addresses long longevity markets such as industrial and biomedical, '''DAVE Embedded Systems''' chose to build BELK /BXELK upon Vivado that undoubtedly represents today the future of Xilinx development environments.
==Structure of BELK /BXELK reference designs==
The typical linux-based Zynq design is composed by the following parts:
==Basic structure of Vivado Design Suite and integration into BELK/BXELK==
Vivado/SDK [1] can be viewed as a collection of programs required to deal with all of the development aspects related to Xilinx components (software running on ARM cores, FPGA fabric verification and programming, power estimation etc.). These include strictly FPGA-related tools such as Floorplanner and pure-software development tools such as SDK.
The ambitious objective is to provide a complete, user friendly, integrated environment that allows software developers to deal with FPGA development even if they are not familiar with this technology, by hiding a lot of its complexities [2]. As usual this ease of use comes at the expence of control and flexibility. This could not be acceptable in many cases where engineers need to control and customize many aspects of the project to implement what is required by system specifications. For this reason BELK has been built around Vivado but some deviations from the default development approach suggested by Xilinx have been introduced, in order to '''push the modularization and the maintainability of the projects to the maximum possible extent'''.
The following pictures are retrieved from BELK Quick Start Guide and shows show respectively the Vivado/SDK default development flow and how this has been integrated in the BELK /BXELK infrastructure.
[[File:Belk-vivado-sdk-development-flow.png|thumbnail|center|300px|Vivado/SDK development flow]]
[[File:Belk-vivado-sdk-integration.png|thumbnail|center|300px|Vivado/SDK integration into BELK/BXELK]]
