{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SOMSoM when it is sold with BoraX. HoweverWhen it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead. Nevertheless, BoarX can host different models of BoraX SOMand Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
==Introduction==
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
The EVB is used also as Evaluation board for the [[:Category:BoraLite | BORA Lite SOM]].
[[File:BoraXEVB-01.png|500px|frameless|border]]
<section begin=Block Diagram/> ==Block Diagram== The following picture shows BORA Xpress EVB block diagram: [[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]===Configurable routing options===FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture. For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]]. ====BoraX====[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]] ====Bora Lite===PL's I/O voltage selections=[[File:Boralite-boraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]] <section end=Block Diagram/>
{|class="wikitable" style="text-align: center;"! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34! colspan="2" style="text-align: center; font-weight: bold;" | Bank #13! colspan="2" style="text-align: center; font-weight: bold;" | Bank #35|-| style="text-align: center; font-weight: bold;" | Type| style="text-align: center; font-weight: bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type| style="text-align: center; font-weight: bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type| style="text-align: center; font-weight: bold;" | I/O voltage setting|-| style="text-align: center;" | 7015(CLG485 package)| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined|-| style="text-align: center;" | 7030(SBG485 package)| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined| style="text-align: center;" | HR(1.2 - 3.3V)| style="text-align: center;" | User defined| style="text-align: center;" | HP(1.2 - 1.8V)| style="text-align: center;" | User defined|}==Block Diagram==The following picture shows BORA Xpress EVB block diagram: [[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]===Configurable routing options===FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture. For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]] == Features ==
* 10/100/1000 Ethernet #0 (PS)
== Connectors pinout ==
<section begin=CPU/>
=== J1,J2 and J3 ===
The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[Pinout (BORAXpress)BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table#Connectors_description|counterpart connectors on BORA Xpress module]].<section end=CPU/><section begin=Power Supply/>
=== Power supply - JP2 ===
|-
|}
<section end=Power Supply/>
<section begin=Reset button/>
=== Reset button - S6 ===
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
<section end=Reset button/>
<section begin=Boot Configurations/>
=== Boot mode selection - S5 ===
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[BORA Lite SOM|BORA Lite]] SOM module
<section end=Boot Configurations/>
<section begin=Watchdog/>
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.
For more details please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Watchdog (BORAXpress)|this page]].
<section begin=JTAG/>== BANK13 VDDIO selector - JP25 = JTAG ===JP25 JTAG port is a 12available as two different mechanical connectors:* 2.00mm-pin 6x2x2pitch 7x2 header (Xilinx standard)* 2.54 54mm-pitch vertical 10x2 header used for the selection - through jumpers - of the bank supply voltages(ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual. The following table reports the pinout of * JTAG on BORA Xpress EVB is also connected to the FMC connector:. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard. ==== JTAG XILINX - J13 ====
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mVThe DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 === BANK35 VDDIO selector = JTAG ARM - JP27 J18 ====JP27 J18 is a 1220-pin 6x2x210x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
The jumper configurations are:# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV# Jumper on 9-10 -<section begin=Console/> adds 100mV to VDDIO_BANK35 above the default 500mV# Jumper on 11=== UART1 -12 -> adds 50mV to VDDIO_BANK35 above the default 500mVJ17 ===
The DEFAULT configuration J17 is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above a standard DB9 connector that routes the signals coming from the default 500mV# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35Please note RS232 transceiver that:* By default VDDIO_BANK35 is supplied by VADJ Regulator=== VADJ VDDIO selector - JP28 ===JP28 is a 12-pin 6x2x2.54 pitch vertical header used for connected to the selection - through jumpers - PS MIO signals of the bank supply voltagesUART1 port. The following table reports the pinout of the connector:
The jumper configurations are:# Jumper on 1-2 -<section begin=USB OTG/> supply VADJ with 3.3V# Jumper on 3=== USB OTG -4 -> supply VADJ with 2.5V# Jumper on 5-6 -> supply VADJ with 1.8V# Jumper on 7-8 -> supply VADJ with 1.5V# Jumper on 9-10 -> supply VADJ with 1.2VJ19 ===
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The DEFAULT configuration isfollowing table reports the pinout of the connector:# Jumper on 5-6 -> supply VADJ with 1.8V
=== JTAG ===JTAG port is available as two different mechanical connectors:* 2.00mm-pitch 7x2 header (Xilinx standard)* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.==== JTAG XILINX - J13 ====J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:{| class="wikitable"
J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
==== JTAG ARM - J18 ====
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|15 13 |3.3V| JTAG_TRSTn|| - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
<section end=micro SD/>
<section begin=DWM/>=== UART1 DWM (DAVE Wifi/BT module) socket - J17 J23 === J17 J23 is a standard DB9 52991-0308 connector that routes type (30 pins, vertical, 0.50mm picth). This socket connects the signals coming from [[DWM_ADD-ON | DWM Wireless Module]] (optional) to the RS232 transceiver that is connected to BORA Xpress EVB. The following table reports the PS MIO signals pinout of the UART1 port.connector:
|7, 8|N.C.|N.C.DWM_SD_CLK |Connected to protection diode array| - || -
|-
|}=== USB OTG 11 ||DWM_SD_DAT0 || - J19 ===J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:{| class="wikitable" | -
J21 === CAN - J24 ===J24 is a microSD memory card connector10-pin 5x2x2. It is 54mm pitch vertical header directly connected to the BORA Xpress SOM through a bidirectional 1SoM's transceiver for the CAN interface.8V/3This 2.3V voltage5mm-level translator mounted on the BORA Xpress EVB. Level shifter pitch header is required because MIO signals are 1.8Vcompatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
|5 ||PS_SD0_CLK||| }<section end=CAN/><section begin=Touchscreen/>=== Touch screen - J25===J25 is a ZIF 4- pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector: {|class="wikitable" | -!Pin# !Pin name!Function!Notes
|-
|6, 9, 10, 11, 12 1 ||DGND|TSC_YP || - || -
|-
|7 2 ||PS_SD0_DAT0|TSC_XP || - || -
|-
|8 3 ||PS_SD0_DAT1|TSC_YM || - || -
|-
|13 4 |3.3V|TSC_XM || - || ||Pull up to 3.3V with 10K Ohm -
|-
|}
<section end=Touchscreen/><section begin=LVDS/>== DWM (DAVE Wifi/BT module) socket = LVDS - J23 J26 ===J23 J26 is a 52991vertical double row straight 20-0308 connector type (30 pinspin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, verticalZynq does not implement an LCD controller, 0however this can be integrated in FPGA fabric as shown by this example: https://wiki.50mm picth)analog. This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the BORA Xpress EVBcom/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.
=== CAN - J24 ===Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPCJ24 * partially compliant to FMC HPC because HPC side is a 10-pin 5x2x2not fully populated.54mm pitch vertical header directly connected to The following tables detail how BORA Xpress SoM's transceiver for the CAN interfacesignals have been routed to FMC connector. This 2At this [[:File:BoraXEVB-FMC-routing.5mm-pitch header zip|link]] a spreadsheet providing the same information is compatible with commonly available IDCfor download. For more information about I/O voltage of single-10ended signals available on FMC connector, please refer to [[#PL's I/DB9 flat cablesO voltage selections|this section]]. The following table reports the pinout of the connector: ==== HPC Row A ====
|}=== Touch screen - J25===J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector:{A5||DGND||GND|| class="wikitable"
|}=== LVDS - J26 ===J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:{A11||MGTxRXN3||DP3_M2C_N|| class="wikitable"
|}=== FPGA Mezzanine Card (FMC) Connector - J27 ===J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.Please note that BoraXpress EVB FMC Connector is:* fully compliant to FMC LPC* partially compliant to FMC HPC because HPC side is not fully populated.The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zipA26||MGTxTXP2||DP2_C2M_P|link]] a spreadsheet providing the same information is available for download.==== HPC Row A ===={| class="wikitable"
| K13K40||IO_25_VRP_35<span style="color:#ff0000">not connected</span>||HA10_PVIO_B_M2C|||}<section end=FMC/><section begin=PinStrip/>=== Pin strip connectors === ==== SPI,NAND - JP13 ==== JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
| K24||DGND||GND|} ==== Voltage Monitor - JP15 ==== JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {|class="wikitable"
=== Pin strip connectors ======= SPI,NAND Ethernet GPIO - JP13 JP18 ==== JP13 JP18 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
==== Voltage Monitor SPI,NAND - JP15 JP19 ==== JP15 JP19 is a 1612-pin 8x2x26x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
<section begin=RTC/><section end=PinStrip/>==== Ethernet GPIO FPGA, WatchDog, RTC, RST - JP18 JP22 ====JP18 JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
JP29 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
==== SPI,NAND - JP19 ====JP19 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
Please note that: * Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption ==== FPGAADC - JP30, WatchDogJP31, RTC, RST - JP22 JP32 ====JP22 is a JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following table tables reports the pinout of the connectorconnectors:
Please note that:* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA** resistive touch screen controller for LCD screen** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption==== ADC - JP30, JP31, JP32 ====JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors:JP30:
JP31<section begin=PMOD/>=== Digilent Pmod™ Compatible headers === Please note that:* Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812** http://www.maximintegrated.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector ==== Digilent Pmod™ Compatible - JP17 ==== JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_BANK35_AD5N PMOD_A0 || AD5_N || Mount option-
|-
|4 2 || FPGA_BANK35_AD6P PMOD_A4 || AD6_P || Mount option-
|-
|5 3 || FPGA_BANK35_AD7P PMOD_A1 || AD7_P || Mount option-
|-
|6 4 || FPGA_BANK35_AD6N PMOD_A5 || AD6_N || Mount option-
|-
|7 5 || FPGA_BANK35_AD7N PMOD_A2 || AD7_N || Mount option-
|-
|10 6 || FPGA_BANK35_AD8P PMOD_A6 || AD8_P || Mount option-
|-
|11 7 || FPGA_BANK35_AD9P PMOD_A3 || AD9_P || Mount option-
|-
|12 8 || FPGA_BANK35_AD8N PMOD_A7 || AD8_N || Mount option-
JP32==== Digilent Pmod™ Compatible - JP23 ====JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 || FPGA_BANK35_AD11P PMOD_B0 || AD11_P - || Mount option-
|-
|2 || FPGA_BANK35_AD10N PMOD_B4 || AD10_N - || Mount option-
|-
|3 || FPGA_BANK35_AD11N PMOD_B1 || AD11_N - || Mount option-
=== Digilent Pmod™ Compatible headers JP27 and JP28===These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
Please note that: * Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built ==PL's I/O modules to PL:voltage selections==** http:<section begin=Voltage selections/>PL's I/wwwO banks voltage can be selected via configuration jumpers.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812It is worth remembering that:** http://www.maximintegrated.com/products/evkits/fpga-modules'''each bank must be powered even if none of its I/Os is used'''* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector '''voltage selection must be done before powering up the board'''.
==== Digilent Pmod™ Compatible - JP17 ====The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
JP17 is a 12{| class="wikitable" style="text-align: center;"! rowspan="2" |SoM! rowspan="2" style="text-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connectoralign:center; font-weight: bold;" | Zynq p/n! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34{! colspan="2" style="text-align: center; font-weight: bold;" | classBank #13! colspan="2" style="wikitabletext-align: center; font-weight: bold;" | Bank #35
|-
!Pin# | style="text-align: center; font-weight: bold;" | Type [1]!Pin name| style="text-align: center; font-weight: bold;" | I/O voltage setting!Function| style="text-align: center; font-weight: bold;" | Type [1]!Notes| style="text-align: center; font-weight: bold;" | I/O voltage setting| style="text-align: center; font-weight: bold;" | Type [1]| style="text-align: center; font-weight: bold;" | I/O voltage setting