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== Introduction ==
Naon memory organization and mapping is quite complex, due to DM8148's multiprocessor nature and the availability of several memory devices connected to the processor. This section will provide an overview of such architecture while following sections will describe in more detail memory map for each device. Please refer to [[Naon_SOM#Module_overview:Category:Naon|Naon block diagram]].
About system RAM, DM8148 provides two controllers. Each one can be interfaced to one SDRAM bank through a physical interface called EMIF (EMIF0 and EMIF1). EMIF0 is connected to 32-bit DDR2 SDRAM bank (up to 512 MByte). EMIF1 is not connected to any device, hence is permanently disabled.
