Changes

In case of Gem1 instead, PHY is populated on BoraEVB and BoraXEVB (U9) and it is interfaced to Programmable Logic (PL). Thus it is necessary to enable EMIO routing and to instantiate a GMII to RGMII bridge in PL as per PHY's interface requirement. About MII bus (MDIO, MDC), two different busses are used:*Bora PHY is connected to the signals ETH_MDC and ETH_MDIO (available on BoraEVB at JP18.7 and JP18.9 respectively)**this MII bus is associated to <code>gem0</code>*BoraEVB PHY is connected to PL's IO_L9N_T1_DQS_34 (ETH1_MDC) and IO_L9P_T1_DQS_34 (ETH1_MDIO); these signals are available on BoraEVB at JP18.8 and JP18.10 respectively**this MII bus is connected to <code>gem1</code>**it is worth to remember that a virtual PHY (whose address is 8) is connected to this bus as well; this PHY is implemented in the GMII/RGMII bridge and it is used to configure the bridge at runtime, depending on operating parameters such as the Ethernet physical link speed.