Bureaucrats, dave_user, Administrators
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→Introduction
Several configurations have been tested in order to provide figures that are measured on real-world use cases instead. Please note that Bora platform is so flexible that is virtually impossible to test for all possible configurations and applications on the market. The use cases here presented should cover most of real-world scenarios. However actual customer application might require more power than values reported here. Generally speaking, application specific requirements have to be taken into consideration in order to size power supply unit and to implement thermal management properly.
The following sections describe in details the test beds that have been used. All of them make use of a specific FPGA bistream that has been developed to perform stress tests on Bora platforms [1]. These tests are condicted conducted in a climatic chamber that allows to set environment temperature surrounding DUT, denoted in the rest of the document as Tamb. Tj denotes Zynq's junction temperature instead.
FPGA bitstream - that in turn is built upon [http://opencores.org/project,highload this core] - allocates most of FPGA resources. All of them are clocked by one clock signal whose frequency is selectable by processor - also denoted as Processing System or PS for short - at runtime. This allows to flexibly change DUT current absorption and, consequently, generated heat.
[1] These tests verify proper operating of the DUT under extremely heavy conditions of usage. Data here reported have been excerpted from the logs generated by such tests.
==Configuration #1==
===Testbed===
