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Voltage references for single-ended I/O signals the same for all configurations. They are detailed in the following table.
{|class="wikitable" style="text-align: center;"
| SNVS_TAMPER[9:0]||VDD_SNVS_IN||143||3.0
|}
'''What is interfaced to 3.3V signals at carrier board level may be referenced to a different voltage than 3.3V_IO. However, the difference between this voltage and 3.3V_IO must not exceed 300mV.'''
*one of the following ordering codes is used: <code>DA p l r n c '''0''' t s</code>, <code>DA p l r n c '''1''' t s</code> or <code>DA p l r n c '''3''' t s</code>
*the same voltage rail is used to power AXEULite SOM and 3.3V carrier board circuitrythis constraint is automatically satisfied.
Since powering is strictly related to reset signals, reading of [[Reset_scheme_(AXELULite)|this page]] is highly recommended.
