Bureaucrats, dave_user, Administrators
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→PL subsystem
Video frames encapsulated in AXI4 streams are then stored - by AXI-VDMAs not shown in the picture - in two independent buffers, both implemented on SDRAM bank #1 (this 16-bit wide bank refers to U14 component of BoraEVB board). Frames are then retrieved by AXI-VDMAs from these buffers and are forwarded to [http://www.xilinx.com/products/intellectual-property/ef-di-osd.html Xilinx On-Screen Display LogiCORE IP block] (named ''video mixer'' in the diagram) that mixes them. The resulting stream in processed by ''LCD controller #1'' module that converts it to TMDS signals feeding the external monitor.
The ''latency gauge'' module is used to perform video latency measurement. Specifically, it is used to measure the time it takes a frame takes to traverse the entire video chain, from the input to the output interface.
To satisfy requirement [[#FR3|[FR3]]], a second controller (''LCD controller #0'' in the diagram) is instantiated, feeding a 7" LVDS LCD. LVDS signals are generated by the FPGA directly.
