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The ''latency gauge'' module is used to perform video latency measurement. Specifically, it is used to measure the time it takes a frame to traverse the entire video chain, from the input to the output interface.
To satisfy requirement [[#FR1FR3|FR1FR3]], a second controller (''LCD controller #0'' in the diagram) is instantiated. It feeds , feeding a 7" LVDS LCD. LVDS signals are generated by the FPGA directly.
===PS subsystem===
*short FreeRTOS domain boot time
*quick PL programming performed by FSBL
allows to minimize the video processing enabling time upon power-on (requirement [[#SR1|SR1]]).
===Notes about SDRAM banks organization===
The block diagram shows two distinct SDRAM banks. Bank #0 is 32-bit wide and includes memory regions used by FreeRTOS and by Linux. It is also used to implement the frame buffer associated to 7" LCD screen. Bank #1 is 16-bit wide and it is used to implement frame buffer for HDMI screen only. Bank #0 is accessed via Zynq's native DDR memory controller. Bank #1 is accessed via memory controller instantiated in PL and created by [http://www.xilinx.com/products/intellectual-property/mig.html|Memory Interface Generator (MIG)].
[1] For example because a misconfiguration caused by a software bug in Linux drivers or by malicious code injected by an attacker.
===Video latency and SDRAM arbitering===
Apart from requirement [[#SR2|SR2]], the availability of two independent SDRAM banks provides an advantage in terms of performances too.
==Future work==
