Bureaucrats, dave_user, Administrators
4,650
edits
Changes
no edit summary
== Introduction ==
This white paper describes a video processing system that has been built upon Bora/BoraEVB. It combines different techniques This system has functional and safety requirements that are available on Zynq platform have to implement a hardware/software partitioning on a video processing be satisfied.
From the functional point of view, it is required to (FR denotes a functional requirement):
*<span id="FR1">FR1</span> acquire two independent video streams
*<span id="FR2">FR2</span> mix the input stream and visualize them on a HDMI monitor
*<span id="FR3">FR3</span> visualize informational and statistical data on an 7" LVDS TFT LCD.
Safety requirements (SR for short) are:
*<span id="SR1">SR1</span>FR1 and FR2 have to be enabled as quickly as possible upon power-up
*<span id="SR1">SR1</span>apart from initialization, FR1 and FR2 have to be independent on the execution of the software; in other words, they keep to be satisfied even if software hangs.
The implementation combines different techniques that are available on Zynq platform to implement a hardware/software partitioning that allows to meet system requirements.
==Implementation==
The following picture shows a simplified block diagram of the entire system [1].
[[File:Bora-dual-video-controller-bd.png|thumb|center|400px|Concept block diagram of the system without monitoring subsystem]]
At hardware level, the natural PS/PL partitioning has been exploited: the processing video chain is entirely implemented in the PL, while PS domain is used for initializing, supervisioning and informational data visualization.
===PL subsystem===
===PS subsystem===
(for more details see also [[BRX-WP001:_Real-timeness,_system_integrity_and_TrustZone®_technology_on_AMP_configuration|this white paper]])
[1] At the time of this writing not all of the shown modules have been completed.
==References==
{{reflist}}
