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→Interrupt latency
* PMIC-based: in this case an external Power Management Integrated Circuit (PMIC) is used to change processor's voltages
* internal LDOs-based: in this case processor's internal linear regulators are used to change such voltages.
PMIC is connected to the processor via I2C bus. As such, every time a transaction is needed, several packets need to be transmitted over I2C bus, resulting in a relatively slow overall transaction time. This may lead to an increase of maximum interrupt latency. In case LDOs-based approach is adopted instead, transactions are quicker because LDOs configuration registers are directly accessible in the processor's address space. On the other hand, the use of LDOs has a significant drawback as explained in the following section.
Please note that OPP transactions may be prevented at all by manually configuring the governor in order to use a fixed OPP.
