Changes

Thanks to the migration to linux kernel 3.10.17, [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|BELK 2.2.0]] and [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|BELK 3.0.0]] allows to cleanly support dual Gigabit Ethernet configuration on BoraEVBand BoraXEVB. This application note describes how to implement such configuration, providing a reference design for Vivado 2014.4 and linux kernel configuration instructions.

First Ethernet port refers to J8 connector of BoraEVB and BoraXEVB carrier board and is based on Zynq's Gigabit Ethernet Controller 0 (Gem0). This controller is mapped at physical address 0xE000B000.

Second Ethernet port refers to J9 connector of BoraEVB and BoraXEVB carrier board and is based on Zynq's Gigabit Ethernet Controller 1 (Gem1). This controller is mapped at physical address 0xE000C000.

The fundamental difference between the two interfaces is the PHY interfacing. In case of Gem0, PHY is mounted on Bora and BoraX SoM and it is interfaced directly to Processor Subsystem (PS) via MIO pads. In case of Gem1 instead, PHY is populated on BoraEVB and BoraXEVB (U9) and it is interfaced to Programmable Logic (PL) pads that belong to bank #34. Thus it is necessary to enable EMIO routing and to instantiate a GMII to RGMII bridge in PL as per PHY's interface requirement. Since bank #34 is powered at 3.3V (High Range I/O mode), RGMII duty cycle distortion specification is not matched. In case of carrier board designed for production environments, <u>it is recommended to use a lower voltage levels and thus a different PL bank</u>. For more details please see section ''I/O Standard and Placement'' of [http://xgoogle.xilinx.com/search?output=xml_no_dtd&ie=UTF-8&oe=UTF-8&getfields=*&filter=0&site=EntireSite&num=200&client=xilinx&proxystylesheet=xilinx&show_dynamic_navigation=0&allVersions=1&sort=meta:Last%2520Modified%2520Date%3AD%3AED&q=+inmeta:Document%2520Class%3DDocument+inmeta:Product%2520Type%3DIP%2520Cores+inmeta:IP%3DGMII%2520to%2520RGMII ''PG160 GMII to RGMII LogiCORE IP Product Guide''] and [[Power_(Bora)|this page]].

===BoraEVB===On BoraEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #34. Here is the pinout assignment for the PHY1 on BoraEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORA SOM Signal'''|-| ETH1_TXD0||IO_L24P_T3_34|-| ETH1_TXD1||IO_L24N_T3_34|-| ETH1_TXD2||IO_L23P_T3_34|-| ETH1_TXD3||IO_L23N_T3_34|-| ETH1_TXCK||IO_L20P_T3_34|-| ETH1_TXCTL||IO_L20N_T3_34|-| ETH1_RXD0||IO_L5N_T0_34|-| ETH1_RXD1||IO_L5P_T0_34|-| ETH1_RXD2||IO_L7N_T1_34|-| ETH1_RXD3||IO_L7P_T1_34|-| ETH1_RXCK||IO_L4N_T0_34|-| ETH1_RXCTL||IO_L4P_T0_34|-| ETH1_MDC||IO_L9N_T1_DQS_34|-| ETH1_MDIO||IO_L9P_T1_DQS_34|-|} Since bank #34 is powered at 3.3V (High Range I/O mode), RGMII duty cycle distortion specification is not matched. In case of carrier board designed for production environments, <u>it is recommended to use a lower voltage levels and thus a different PL bank</u>. For more details please see section ''I/O Standard and Placement'' of [http://xgoogle.xilinx.com/search?output=xml_no_dtd&ie=UTF-8&oe=UTF-8&getfields=*&filter=0&site=EntireSite&num=200&client=xilinx&proxystylesheet=xilinx&show_dynamic_navigation=0&allVersions=1&sort=meta:Last%2520Modified%2520Date%3AD%3AED&q=+inmeta:Document%2520Class%3DDocument+inmeta:Product%2520Type%3DIP%2520Cores+inmeta:IP%3DGMII%2520to%2520RGMII ''PG160 GMII to RGMII LogiCORE IP Product Guide''] and [[Power_(Bora)|this page]]. The project archive can be downloaded '''TBD''' <nowiki>[http://www.dave.eu/system/files/area-riservata/AN-BELK-006-xpr.zip here].</nowiki> ===BoraXEVB===On BoraXEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #13. Here is the pinout assignment for the PHY1 on BoraXEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORAX SOM Signal'''|-| ETH1_TXD0||IO_L19P_T3_13|-| ETH1_TXD1||IO_L19N_T3_VREF_13|-| ETH1_TXD2||IO_L20P_T3_13|-| ETH1_TXD3||IO_L20N_T3_13|-| ETH1_TXCK||IO_L16P_T2_13|-| ETH1_TXCTL||IO_L16N_T2_13|-| ETH1_RXD0||IO_L17P_T2_13|-| ETH1_RXD1||IO_L17N_T2_13|-| ETH1_RXD2||IO_L18P_T2_13|-| ETH1_RXD3||IO_L18N_T2_13|-| ETH1_RXCK||IO_L15P_T2_DQS_13|-| ETH1_RXCTL||IO_L15N_T2_DQS_13|-| ETH1_MDC||IO_L21N_T3_DQS_13|-| ETH1_MDIO||IO_L21P_T3_DQS_13|-|} I/O voltage of bank 13 must be set to 2.5V by configuring [[BoraXEVB#BANK13_VDDIO_selector_-_JP25|JP25 ]] as shown in the following table.{| class="wikitable" border="1"!Pins!Setting|-|1-2|closed|-|3-4|open|-|5-6|closed|-|7-8|open|-|9-10|open|-|11-12|open|-|} The project archive can be downloaded '''TBD''' <nowiki>[http://www.dave.eu/system/files/area-riservata/AN-BELK-006-xpr.zip here].</nowiki>