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Changes
→Feature Summary
| CPU|| Xilinx Dual ARM Cortex-A9 ZYNQ XC7Z015/ZC7Z030 @ up to 1GHz ||
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| RAMCache|| 32 Kbyte instruction, 32 Kbyte data, 512 Kbyte L2 for each core ||
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| StorageSDRAM||Cache: 32 Kbyte instruction, 32 Kbyte data, 512 Kbyte L2 for each core <br> SDRAM: up to 1GB DDR3 @ 533 MHz <br> |||-| NOR: || Bootable SPI NOR 8, 16 MB <br> |||-| NAND: || All sizes, on request||
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| External local bus|| ||
