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Conclusions and future work
==Conclusions and future work==
As result The following conclusions can be drawn from those the test we can say thatresults:* Linux activity on CPU/memory/SD does not virtually has no influence on RTOS latency* minimal Moderate RTOS activity have has no impact on latency.* a bigger RTOS activityAs expected, in this case on main array size is much bigger than L1 memorysize, have some impact on data/instruction cache misses increase significantly resulting in higher latency, mainly the ARM core observe more L1 cache miss on both data and instructions.
===Isolation vs performances===
This work confirmed the need to find a trade-off between two requirements that often push in opposite directions: isolation and performances. On one hand isolation should be pushed to the maximum possible extent to preserve the integrity of W1 world. On the other hand, overall systems performances have not to be affected so much that the product gets unusable. Generally speaking, strong isolation negatively impacts performances, so finding the optimal balancing is not trivial. A "one size fits all" solution does not exist and system designer is responsible to choose which direction this knob has to be moved. This analysis naturally has to take into account application-specific requirements.
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