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BoraXEVB

21,767 bytes added, 15:04, 4 November 2015

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[[File:Boraxevb.png|650px|frameless|border]]

==Introduction==

Bora Xpress EVB is a carrier board designed to host [[BoraXpress SOM|Bora Xpress system-on-module]].

==Block Diagram==

The following picture shows Bora Xpress EVB block diagram:

[[File:Boraxevb-bd.png]]

== Features ==

* 10/100/1000 Ethernet #0 (PS)

* 10/100/1000 Ethernet #1 (Routed through EMIO)

* 1x USB 2.0 OTG (MicroAB connector)

* 1x Serial port (RS232 DB9)

* 1x MicroSD

* 1x FPGA Mezzanine Card (FMC) Connector

* XADC

** Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connectors, instead of FMC connector.

* State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA

* JTAG port

* Socket for [[Wireless_Module_(DWM) | DWM Wireless Module]]

* Digilent Pmod™ Compatible expansion connectors

* Headers for external for NAND flash and SPI NOR flash

* 2.54mm-pitch pin-strip connectors for Bora Xpress PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)

* Jumpers for voltage selection of the PL banks

* +12V power connector

== Known limitations ==

Board version CS040713A has the following limitations:

{| class="wikitable"

|-

!Issue

!Description

|-

| LCD_BKLT_PWM I/O voltage

| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.

|-

|}

== Connectors pinout ==

=== J1 ===

The pinout of the J1 connector of the Bora Xpress EVB is the same of the J1 connector on BORA Xpress module

=== J2 ===

The pinout of the J2 connector of the Bora Xpress EVB is the same of the J2 connector on BORA Xpress module

=== J3 ===

The pinout of the J3 connector of the Bora Xpress EVB is the same of the J3 connector on BORA Xpress module

=== Power supply - JP2 ===

Power is provided through the JP2 connector.

JP2 connector is a standard 2.1mm/5.5mm DC power jack with positive center pin

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || VIN || Power supply || Nominal: +12V

|-

|2 , 3 || DGND || Ground || -

|-

|}

=== Boot mode selection - S5 ===

S5 is a dip-switch for the boot mode selection. The following table reports the available options and the related configurations:

{| class="wikitable"

|-

! !! S5.1 !! S5.2 !! S5.3 !! S5.4 !! S5.5 !! S5.6 !! S5.7 !! S5.8

|-

| SPI-NOR || OFF || ON || OFF || ON || ON || ON || ON || OFF

|-

| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF

|-

| NAND || OFF || ON || OFF || ON || ON || OFF || ON || ON

|-

| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON

|}

=== Ethernet port #0 (ETH0) - J8 ===

J8 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to the Bora Xpress integrated ethernet controller and PHY.

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || CT_TRD3 || center tap TRD3 || -

|-

|2 || ETH_TXRX2_M || - || -

|-

|3 || ETH_TXRX2_P || - || -

|-

|4 || ETH_TXRX1_P || - || -

|-

|5 || ETH_TXRX1_M || - || -

|-

|6 || CT_TRD2 || center tap TRD2 || -

|-

|7 || CT_TRD4 || center tap TRD4 || -

|-

|8 || ETH_TXRX3_P || - || -

|-

|9 || ETH_TXRX3_M || - || -

|-

|10 || ETH_TXRX0_M || - || -

|-

|11 || ETH_TXRX0_P || - || -

|-

|12 || CT_TRD1 || center tap TRD1 || -

|-

|13 || 3.3V_ETH0_LED2 || - || -

|-

|15 || 3.3V_ETH0_LED1 || - || -

|-

|14, 16 || +3.3V || - || -

|-

|}

=== Ethernet port #1 (ETH1) - J9 ===

J9 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to Micrel KSZ9031 PHY (Gigabit Ethernet Transceiver). This, in turn, is connected to PL's bank 13 via RGMII interface. This is an example of EMIO routing showing how to route PS's MAC signals via PL subsystem.

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || CT_TRD3 || center tap TRD3 || -

|-

|2 || ETH1_TXRX2_M || - || -

|-

|3 || ETH1_TXRX2_P || - || -

|-

|4 || ETH1_TXRX1_P || - || -

|-

|5 || ETH1_TXRX1_M || - || -

|-

|6 || CT_TRD2 || center tap TRD2 || -

|-

|7 || CT_TRD4 || center tap TRD4 || -

|-

|8 || ETH1_TXRX3_P || - || -

|-

|9 || ETH1_TXRX3_M || - || -

|-

|10 || ETH1_TXRX0_M || - || -

|-

|11 || ETH1_TXRX0_P || - || -

|-

|12 || CT_TRD1 || center tap TRD1 || -

|-

|13 || 3.3V_ETH1_LED2 || - || -

|-

|15 || 3.3V_ETH1_LED1 || - || -

|-

|14, 16 || +3.3V || - || -

|-

|}

=== BANK's GOOD signals - J28 ===

J28 is a 10-pin 5x2x2.54 pitch vertical header used for accessing to the POWER GOOD signals. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 , 3 || 3.3V_SOM|| - || -

|-

|2 || SOM_PGOOD|| - || -

|-

|4 || 1.8V_POWER_GOOD || - || -

|-

|5 || 3.3V_SBY || - || -

|-

|6 || VADJ_PG || - || -

|-

|7 || BANK13_PGOOD || - || -

|-

|8 || BANK35_PGOOD || - || -

|-

|9 || 1V2_ETH1_PG || - || -

|-

|10 || DGND || - || -

|-

|}

=== BANK13 VDDIO selector - JP25 ===

JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|2 || LDO_B13_1V6|| adds +1.6V to VDDIO_BANK13 || -

|-

|4 || LDO_B13_800mV|| adds +800mV to VDDIO_BANK13 || -

|-

|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -

|-

|8 || LDO_B13_200mV|| adds +200mV to VDDIO_BANK13 || -

|-

|10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -

|-

|12 || LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -

|-

|1, 3, 5, 7, 9, 11 || DGND|| - || -

|-

|}

The jumper configurations are:

# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV

# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV

# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV

# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV

# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV

# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV

# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV

The DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):

# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV

# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13

# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13

=== BANK35 VDDIO selector - JP27 ===

JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -

|-

|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -

|-

|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -

|-

|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -

|-

|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -

|-

|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -

|-

|1, 3, 5, 7, 9, 11 || DGND|| - || -

|-

|}

The jumper configurations are:

# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV

# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV

# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV

# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV

# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV

# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV

# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV

The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):

# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV

# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35

# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35

=== VADJ VDDIO selector - JP28 ===

JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -

|-

|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -

|-

|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -

|-

|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -

|-

|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -

|-

|12 || RFU|| Reserved || -

|-

|1, 3, 5, 7, 9, 11 || DGND|| - || -

|-

|}

The jumper configurations are:

# Jumper on 1-2 -> supply VADJ with 3.3V

# Jumper on 3-4 -> supply VADJ with 2.5V

# Jumper on 5-6 -> supply VADJ with 1.8V

# Jumper on 7-8 -> supply VADJ with 1.5V

# Jumper on 9-10 -> supply VADJ with 1.2V

The DEFAULT configuration is:

# Jumper on 5-6 -> supply VADJ with 1.8V

=== JTAG ===

JTAG port is available as two different mechanical connectors:

* 2.00mm-pitch 7x2 header (Xilinx standard)

* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf

* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.

* JTAG on Bora Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.

==== JTAG XILINX - J13 ====

J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 3, 5, 7, 9, 11, 13 || DGND|| - || -

|-

|2 || 3.3V|| - || -

|-

|4 || JTAG_TMS|| - || -

|-

|6 || JTAG_TCK|| - || -

|-

|8 || JTAG_TDO|| - || -

|-

|10 || JTAG_TDI|| - || -

|-

|12 || N.C.|| - || -

|-

|14 || JTAG_TRSTn|| - || -

|-

|}

==== JTAG ARM - J18 ====

J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || 3.3V|| - || -

|-

|2 || 3.3V|| - || -

|-

|3, 11, 17, 19 || N.C.|| - || -

|-

|4, 6 ,8 ,10 ,12, 14, 16, 18, 20|| DGND|| - || -

|-

|5 || JTAG_TDI|| - || -

|-

|7 || JTAG_TMS|| - || -

|-

|9 || JTAG_TCK|| - || -

|-

|13 || JTAG_TDO|| - || -

|-

|15 || JTAG_TRSTn|| - || -

|-

|}

=== UART1 - J17 ===

J17 is a standard DB9 connector that routes the signals coming from the RS232 transceiver that is connected to the PS MIO signals of the UART1 port.

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 6, 4, 9

|N.C.

|

|-

|2

|UART_EXT_RX

|Receive line

|Connected to protection diode array

|-

|3

|UART_EXT_TX

|Transmit line

|Connected to protection diode array

|-

|5

|DGND

|Ground

|

|-

|7, 8

|N.C.

|Connected to protection diode array

|-

|}

=== USB OTG - J19 ===

J19 is a standard USB MICRO AB connector. It is connected to the Bora Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 ||USB_OTG_VBUS || - || -

|-

|2 ||USBM1 || - || -

|-

|3 ||USBP1 || - || -

|-

|4 ||OTG_ID || - || -

|-

|5 ||USB_OTG_DGND || - || -

|-

|6, 7, 8, 9 ||USB_OTG_SHIELD || - || -

|-

|}

=== MicroSD - J21 ===

J21 is a microSD memory card connector. It is connected to the Bora Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the Bora Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 ||PS_SD0_DAT2||| - || -

|-

|2 ||PS_SD0_DAT3||| - || -

|-

|3 ||PS_SD0_CMD||| - || -

|-

|4 ||3.3V||| - || -

|-

|5 ||PS_SD0_CLK||| - || -

|-

|6, 9, 10, 11, 12 ||DGND||| - || -

|-

|7 ||PS_SD0_DAT0||| - || -

|-

|8 ||PS_SD0_DAT1||| - || -

|-

|13 |3.3V||| - || ||Pull up to 3.3V with 10K Ohm -

|-

|}

=== DWM (DAVE Wifi/BT module) socket - J23 ===

J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the Bora Xpress EVB. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 2 ||5V || - || -

|-

|3, 4 ||3.3V || - || -

|-

|5, 6, 9, 10, 19 ||DGND || - || -

|-

|7 ||DWM_SD_CMD || - || -

|-

|8 ||DWM_SD_CLK || - || -

|-

|11 ||DWM_SD_DAT0 || - || -

|-

|12, 14, 16, 18, 20, 22 ||N.C. || - || -

|-

|13 ||DWM_SD_DAT1 || - || -

|-

|15 ||DWM_SD_DAT2 || - || -

|-

|17 ||DWM_SD_DAT3 || - || -

|-

|21 ||DWM_UART_RX || - || -

|-

|23 ||DWM_UART_CTS || - || -

|-

|24 ||DWM_BT_F5 || - || -

|-

|25 ||DWM_UART_TX || - || -

|-

|26 ||DWM_BT_F2 || - || -

|-

|27 ||DWM_UART_RTS || - || -

|-

|28 ||DWM_WIFI_IRQ || - || -

|-

|29 ||DWM_BT_EN || - || -

|-

|30 ||DWM_WIFI_EN || - || -

|-

|}

=== CAN - J24 ===

J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 6, 7, 8, 9, 10 ||N.C. || - || -

|-

|2, 5 ||CAN_SHIELD || - || -

|-

|3 ||CAN_L || - || -

|-

|4 ||CAN_H || - || -

|-

|}

=== Touch screen - J25===

J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the Bora Xpress EVB. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 ||TSC_YP || - || -

|-

|2 ||TSC_XP || - || -

|-

|3 ||TSC_YM || - || -

|-

|4 ||TSC_XM || - || -

|-

|}

=== LVDS - J26 ===

J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 2 ||3.3V_LCD || - || -

|-

|3, 4, 7, 10, 13, 16, 19 ||DGND || Ground || -

|-

|5 ||LCD_LVDS_D0- || - || -

|-

|6 ||LCD_LVDS_D0+ || - || -

|-

|8 ||LCD_LVDS_D1- || - || -

|-

|9 ||LCD_LVDS_D1+ || - || -

|-

|11 ||LCD_LVDS_D2- || - || -

|-

|12 ||LCD_LVDS_D2+ || - || -

|-

|15 ||LCD_LVDS_CLK+ || - || -

|-

|17 ||LCD_P17 || - || -

|-

|18 ||LCD_P18 || - || -

|-

|20 ||LCD_P20 || - || -

|-

|21,22 ||DGND || Ground || Shield

|-

|}

=== Pin strip connectors ===

==== ADC - JP30, JP31, JP32 ====

JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors:

JP30:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || IO_0_35 || - || -

|-

|2, 4 || VDDIO_BANK35 || - || -

|-

|3, 6, 9, 12, 15 || XADC_GND || - || -

|-

|5 || ZYNQ_AD14P_35 || - || Mount option

|-

|7 || ZYNQ_AD14N_35 || - || Mount option

|-

|8 || ZYNQ_T0_VREF_35 || - || Mount option

|-

|10 || ZYNQ_T3_VREF_35 || - || Mount option

|-

|11 || ZYNQ_AD1P_35 || - || Mount option

|-

|13 || ZYNQ_AD1N_35 || - || Mount option

|-

|14 || ZYNQ_AD3P_35 || - || Mount option

|-

|16 || ZYNQ_AD3N_35 || - || Mount option

|-

|}

==== SPI,NAND - JP13 ====

JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 4, 9, 12 || DGND || Ground || -

|-

|2 || SPI0_CS0n || - || -

|-

|3 || ZYNQ_SPI0_SCLK/NAND_IO1 || - || -

|-

|5 || ZYNQ_SPI0_DQ0/NAND_ALE || - || -

|-

|6 || NAND_CS0/SPI0_CS1 || - || -

|-

|7 || ZYNQ_SPI0_DQ2/NAND_IO2 || - || -

|-

|8 || ZYNQ_SPI0_DQ1/NAND_WE || - || -

|-

|10 || ZYNQ_SPI0_DQ3/NAND_IO0 || - || -

|-

|11 || ZYNQ_NAND_RD_B || - || -

|-

|}

==== Voltage Monitor - JP15 ====

JP15 is a 12-pin 6x2x2.00 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || MON_VCCPLL || - || -

|-

|2 || MON_3.3V || - || -

|-

|3 || MON_XADC_VCC || - || -

|-

|4 || MON_1V2_ETH || - || -

|-

|5 || MON_FPGA_VDDIO_BANK35 || - || -

|-

|6 || MON_VDDQ_1V5 || - || -

|-

|7 || MON_FPGA_VDDIO_BANK34 || - || -

|-

|8 || MON_1.8V || - || -

|-

|9 || MON_FPGA_VDDIO_BANK13 || - || -

|-

|10 || MON_1.0V || - || -

|-

|11 || MON_1.8V_IO || - || -

|-

|12 || DGND || Ground || -

|-

|}

==== Ethernet GPIO - JP18 ====

JP18 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 11, 12|| DGND || Ground || -

|-

|2 || NAND_BUSY|| - || -

|-

|3 || ZYNQ_NAND_CLE || - || -

|-

|4 || NAND_IO3 || - || -

|-

|5 || NAND_IO4 || - || -

|-

|6 || NAND_IO5 || - || -

|-

|7 || NAND_IO6 || - || -

|-

|8 || NAND_IO7 || - || -

|-

|9 || CONN_SPI_RSTn || - || -

|-

|10 || MEM_WPn || - || -

|-

|}

==== SPI,NAND - JP19 ====

JP19 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1, 2, 5, 6, 16|| DGND || Ground || -

|-

|3 || CLK125_NDO|| - || -

|-

|4 || ETH1_CLK125_NDO || - || -

|-

|7 || ETH_MDC || - || -

|-

|8 || ETH1_MDC || - || -

|-

|9 || ETH_MDIO || - || -

|-

|10 || ETH1_MDIO || - || -

|-

|11 ||ETH_INTn || - || -

|-

|12 || ETH1_INTn || - || -

|-

|13 || PS_MIO51_501 || - || -

|-

|14 || ETH1_RESETn || - || -

|-

|15 || PS_MIO50_501 || - || -

|-

|}

==== ADC - JP20 ====

JP20 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || VDDIO_BANK35|| - || -

|-

|2, 6, 11, 12 || XADC_AGND || - || -

|-

|3 || ZYNQ_AD0P_35 || - || -

|-

|4 || MON_XADC_VCC || - || -

|-

|5 || ZYNQ_AD15P_35 || - || -

|-

|7 || ZYNQ_AD15N_35 || - || -

|-

|8 || XADC_VN_R || - || -

|-

|9 || ZYNQ_AD2P_35 || - || -

|-

|10 || XADC_VP_R || - || -

|-

|}

==== I2C, BANK34 - JP21 ====

JP21 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || EVB_1.8V || - || -

|-

|2 || 3.3V || - || -

|-

|3 || PS_I2C0_DAT|| - || -

|-

|4 || I2C0_SDA || - || -

|-

|5 || PS_I2C0_CK || - || -

|-

|6 || I2C0_SCL || - || -

|-

|7, 8, 12, 13 || DGND || Ground || -

|-

|9 || IO_L6P_T0_34 || CAN Transmitter || -

|-

|10 || INA_ALERT || - || -

|-

|11 || IO_L19P_T3_34 || CAN Receiver || -

|-

|14 || IO_L3P_T0_DQS_PUDC_B_34 || - || -

|-

|15 || IO_25_34 || - || -

|-

|16 || IO_0_34 || - || -

|-

|}

Please note that:

* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):

** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA

** resistive touch screen controller for LCD screen

** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption

==== FPGA, WatchDog, RTC, RST - JP22 ====

JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 || FPGA_INIT_B|| - || -

|-

|2 || RTC_32KHZ || - || -

|-

|3 || FPGA_PROGRAM_B|| - || -

|-

|4 || RTC_RST || - || -

|-

|5 || FPGA_DONE || - || -

|-

|6 || RTC_INT/SQW || - || -

|-

|7, 8 || DGND || Ground || -

|-

|9 || WD_SET0 || - || -

|-

|10 || SYS_RSTn || - || -

|-

|11 || WD_SET1 || - || -

|-

|12 || PORSTn || - || -

|-

|13 || WD_SET2 || - || -

|-

|14 || MRSTn || - || -

|-

|15 || PS_MIO15_500 || - || -

|-

|16 || CB_PWR_GOOD || - || -

|-

|}

=== Digilent Pmod™ Compatible headers ===

Please note that:

* Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:

** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812

** http://www.maximintegrated.com/products/evkits/fpga-modules/

* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector

==== Digilent Pmod™ Compatible - JP17 ====

JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 ||PMOD_A0 || || -

|-

|2 ||PMOD_A4 || || -

|-

|3 ||PMOD_A1 || || -

|-

|4 ||PMOD_A5 || || -

|-

|5 ||PMOD_A2 || || -

|-

|6 ||PMOD_A6 || || -

|-

|7 ||PMOD_A3 || || -

|-

|8 ||PMOD_A7 || || -

|-

|9, 10 ||DGND ||Ground || -

|-

|11, 12 ||3.3V || || -

|-

|}

==== Digilent Pmod™ Compatible - JP23 ====

JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

{| class="wikitable"

|-

!Pin#

!Pin name

!Function

!Notes

|-

|1 ||PMOD_B0 || - || -

|-

|2 ||PMOD_B4 || - || -

|-

|3 ||PMOD_B1 || - || -

|-

|4 ||PMOD_B5 || - || -

|-

|5 ||PMOD_B2 || - || -

|-

|6 ||PMOD_B6 || - || -

|-

|7 ||PMOD_B3 || - || -

|-

|8 ||PMOD_B7 || - || -

|-

|9, 10 ||DGND ||Ground || -

|-

|11, 12 ||3.3V || - || -

|-

|}

==Schematics==

* ORCAD: '''TBD''' boraxevb-1.0.2-BELK-dsn.zip

* PDF : '''TBD''' BoraXEVB-S-EVBBX0000C0R-1.2.0.pdf

==BOM==

* BoraXEVB: '''TBD''' boraxevb-BOM_S.EVBBX0000C0R.1.2.0.CSV.zip

==Layout==

* '''TBD''' boraxevb-CS143714_assembly_view.pdf

==Mechanical==

* DXF: '''TBD''' boraxevb_2D_CS143714.zip

* IDF (3D): '''TBD''' boraxevb_3D_CS143714.zip

U0004

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