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This application note describes how to build the software components required to set up asymmetric multi-processing (AMP for short) configuration required to run Linux OS on first Cortex-A9 core and FreeRTOS on second Cortex-A9 core of the Zynq SOC.
Asymmetric Multi Processing Multiprocessing (AMP) allows a multiprocessor/multicore system to run multiple Operating Systems (OS) that are independent of each other. In other words, each CPU has its own private memory space, which contains the OS and the applications that are to run on that CPU. In addition, there can be some shared memory space that is used for multiprocessor communication. This is contrasted with Symmetric Multiprocessing (SMP), in which one OS runs on multiple CPUs using a public shared memory space. Thanks to AMP, developers can use open-source Linux and FreeRTOS operating systems and the RPMsg Inter Processor Communication (IPC) framework between the Zynq's two high-performance ARM® Cortex™-A9 processors to quickly implement applications that need to deliver deterministic, real-time responsiveness for markets such as automotive, industrial and others with similar requirements. For further information, please refer to this [http://www.wiki.xilinx.com/Multi-OS+Support+%28AMP+%26+Hypervisor%29 link].
Two different examples are here provided. The first one – HelloWorld – shows basic functionalities while the second – RPMsg-based application – exploits more sophisticated techniques to handle inter-processors communication and synchronization. This latter configuration is based on RPMsg mechanism as described in Xilinx document UG978 (v2013.04, April 22, 2013).
PDF version of this Application Note can be downloaded [http://www.dave.eu/sites/default/files/files/an-belk-001-amp-linux-freertos.pdf here].
==AMP on Bora==
The following sections detail how to build the software components required to set up asymmetric multi-processing (AMP for short) configuration required to run Linux OS on first Cortex-A9 core and FreeRTOS on second Cortex-A9 core.
The prerequisites are:
* Vivado® Design Suite version 2013.3 with Xilinx SDK (Webpack license is minimum requirements)
* Python 2.7.x (C:\Python27 must be the installation directory on Windows)
* [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|Bora Embedded Linux Kit (Please refer to BELK Quick Start Guide for further details) version 2.0.0]].
* BORA FreeRTOS repository (please refer to section TBD)
===Building the software components===
====Vivado project====
* log into the development host
* Assuming that a local repository has not been created, clone the remote Bora git repository (the <code>-b</code> option is used to automatically checkout the current branch):
<pre>
git clone git@git.dave.eu:dave/bora/bora.git -b bora
</pre>
* Enter the git directory
* Switch to bora branch (not required if this is already the current branch):
<pre>
git checkout bora
</pre>
Set project directory variable:
<pre>
export PROJ_DIR=$(pwd)/../bora-build-YYYYMMDD-nobk
</pre>
Configure Vivado settings (1):
<pre>
. /opt/Xilinx/Vivado/2013.3/settings64.sh
</pre>
Launch Vivado with <code>build_project</code> script (2):
<pre>
vivado -mode tcl -source build_project.tcl -notrace -tclargs "-bitstream"
</pre>
== Documentation ==
