Changes

Thanks to the migration to linux kernel 3.10.17, [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|BELK 2.2.0]] allows to cleanly support dual Gigabit Ethernet configuration on BoraEVB. This application note describes how to implement such configuration, providing a reference design for Vivado 2014.4 and linux kernel configuration instructions.

Simplified block diagram of dual Ethernet congfiuration is shown in the following picture.

In case of Gem1 instead, PHY is populated on BoraEVB (U9) and it is interfaced to Programmable Logic (PL) pads that belong to bank #34. Thus it is necessary to enable EMIO routing and to instantiate a GMII to RGMII bridge in PL as per PHY's interface requirement. Since bank #34 is powered at 3.3V (High Range I/O mode), RGMII duty cycle distortion specification is not matched. In case of carrier board designed for production environments, it is recommended to use a lower voltage levels and thus a different PL bank. For more details please see section ''I/O Standard and Placement'' of [http://xgoogle.xilinx.com/search?output=xml_no_dtd&ie=UTF-8&oe=UTF-8&getfields=*&filter=0&site=EntireSite&num=200&client=xilinx&proxystylesheet=xilinx&show_dynamic_navigation=0&allVersions=1&sort=meta:Last%2520Modified%2520Date%3AD%3AED&q=+inmeta:Document%2520Class%3DDocument+inmeta:Product%2520Type%3DIP%2520Cores+inmeta:IP%3DGMII%2520to%2520RGMII ''PG160 GMII to RGMII LogiCORE IP Product Guide''] and [[Power_(Bora)|this page]].

The following picture shows the block diagram of the Vivado project: