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→Power Supply Unit (PSU) and recommended power-up sequence
# this step is composed of two events
#* main PSU enables several voltage rails to complete CPU, memories and peripheral power up sequence
#* VAUX33 signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board circuitry that interfaces CPU I/O directlyor vice versa)
# PORSTn_OUT signal is raised to indicate that all power rails of SOM are stable
* PWRHOLD (input): This signal is connected to processor's PMIC_PWR_EN and is used to initiate power up sequence.
* PMIC_PWRON (input): A rising edge of this pin (automatically done at startup) the PMIC performs an OFF-to-ACTIVE state transition. On a falling edge of this pin, the PMIC performs an ACTIVE-to-OFF state transition. This signal is pulled-up to VIN through 10kOhm resistor.
== Reset scheme and voltage monitoring ==
Diva implements a flexible reset scheme that offers several different solutions for system integrators at carrier board level. The following picture shows a diagram of the reset scheme:
