[[File:AxelLite-reset-scheme.png | 800px]]
The available === PMIC_VSNVS ===Some signals that are related to reset signals circuitry are described pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's VIN pin** in detail case of AxelLite this pin is connected to 3.3VIN power rail* voltage applied to PMICS's LICELL pin** in the following sectionscase of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)* PMIC's VSNVSCTL register configuration.Hence it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level. For more details please refer to section ''VSNVS LDO/Switch'' of ''MMPF0100 Advance Information'' document.
=== CPU_PORn ===
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
=== Handling CPU initiated reset ===
'''By default, MX6 processor does not assert any external signal when it initiates a reset sequence'''. This behaviour can be changed by acting on WDOG_RESET_B_DEB signal configuration. This signal is driven by MX6's watchdog timer (WDT).
