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Created page with "{{InfoBoxTop}} {{Applies To Bora}} {{InfoBoxBottom}} == Introduction == Bora modules implement a number of peripheral interfaces through the J1, J2 and J3 connectors. The fo..."
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{{Applies To Bora}}
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== Introduction ==
Bora modules implement a number of peripheral interfaces through the J1, J2 and J3 connectors. The following notes apply to those interfaces:
* Some interfaces/signals are available only with/without certain configuration options of the Bora module.
* The peripherals described in the following sections represent the default configuration for the Bora SOM, which match with the features provided by the electronics implemented on the module. As an example, the Zynq device provides two USB 2.0 controllers, but the Bora SOM provides one USB OTG port, with transceiver connected to one of the controllers and signals routed to the module connectors. Therefore, only one USB port will be described in details.
== Notes on pin assignment ==
For detailed information on MIO and EMIO configuration, please refer to section 2.5.1 /“I/O Peripheral (IOP) Interface Routing”) of the Zynq-7000 Technical Reference Manual.
On the Bora SOM, the MIO module is configured for providing a standard set of peripherals (eg, Ethernet, USB, …); some pins of the EMIO are also used to implement some functions (eg: I2C, specific I/Os). Plese refer to the following sections for detailed information.
== PS interfaces ==
The 54 pins of the MIO module are assigned as reported in the following table:
{| class="wikitable"
|-
!MIO Pins
!Function
|-
|MIO[0:14]
|Quad-SPI and NAND flash
|-
|MIO[15]
|EX_WDT_REARM (watchdog WDI)<br>Optionally, it can act as SWDT reset out
|-
|MIO[16:27]
|Gigabit Ethernet
|-
|MIO[28:39]
|USB On-The-Go
|-
|MIO[40:45]
|SD/SDIO/MMC
|-
|MIO[46:47]
|I2C0
|-
|MIO[48:49]
|UART1
|-
|MIO[52]
|Ethernet Management Data Clock input
|-
|MIO[53]
|Ethernet Management Data Input/Output
|-
|}
{{Applies To Bora}}
{{InfoBoxBottom}}
== Introduction ==
Bora modules implement a number of peripheral interfaces through the J1, J2 and J3 connectors. The following notes apply to those interfaces:
* Some interfaces/signals are available only with/without certain configuration options of the Bora module.
* The peripherals described in the following sections represent the default configuration for the Bora SOM, which match with the features provided by the electronics implemented on the module. As an example, the Zynq device provides two USB 2.0 controllers, but the Bora SOM provides one USB OTG port, with transceiver connected to one of the controllers and signals routed to the module connectors. Therefore, only one USB port will be described in details.
== Notes on pin assignment ==
For detailed information on MIO and EMIO configuration, please refer to section 2.5.1 /“I/O Peripheral (IOP) Interface Routing”) of the Zynq-7000 Technical Reference Manual.
On the Bora SOM, the MIO module is configured for providing a standard set of peripherals (eg, Ethernet, USB, …); some pins of the EMIO are also used to implement some functions (eg: I2C, specific I/Os). Plese refer to the following sections for detailed information.
== PS interfaces ==
The 54 pins of the MIO module are assigned as reported in the following table:
{| class="wikitable"
|-
!MIO Pins
!Function
|-
|MIO[0:14]
|Quad-SPI and NAND flash
|-
|MIO[15]
|EX_WDT_REARM (watchdog WDI)<br>Optionally, it can act as SWDT reset out
|-
|MIO[16:27]
|Gigabit Ethernet
|-
|MIO[28:39]
|USB On-The-Go
|-
|MIO[40:45]
|SD/SDIO/MMC
|-
|MIO[46:47]
|I2C0
|-
|MIO[48:49]
|UART1
|-
|MIO[52]
|Ethernet Management Data Clock input
|-
|MIO[53]
|Ethernet Management Data Input/Output
|-
|}
