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Carrier board design guidelines (SOM)

763 bytes added, 14:48, 9 January 2014
I2C Interface
* Isolate I2C clock from noise sensitive signals
* Avoid stub
=== SD Interface ===
 
{| class="wikitable" border="1"
| align="center" style="background:#f0f0f0;"|''' '''
| align="center" style="background:#f0f0f0;"|''' Value '''
| align="center" style="background:#f0f0f0;"|''' u.m. '''
|-
| Matching required*||align="center"|-||
|-
| Max allowed parallel routing||align="center"|1000||align="center"|mils
|-
| Max trace Length**||align="center"|-||
|-
| Max # of vias allowed||align="center"|-||
|-
|}
<nowiki>*</nowiki>This is not mandatory, however it is suggested in case trace length exceeds 10cm
 
<nowiki>**</nowiki>Overall trace length - i.e. Bora + carrier board - should not exceed 10cm. If this is not possible, try to avoid parallel routing in order to reduce crosstalk, and refer them to a ground plane.
 
==Functional guidelines==
===Sudden power off management===

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