3,260
edits
Changes
m
→Watchdog
An external watchdog (MAX6373 device) is connected to the AM335X_GMII1_TXD2 (J1.159) signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI (AM335X_GMII1_TXD2) before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP.
The MAX6373 watchdog timer is pin-selectable and the timer can be configured through the WD_SET0 (J1.7), WD_SET1 (J1.9) and WD_SET2 (J1.11) signals. As a default, the watchdog is configured through a pull-up/pull-down resistors network (WD_SET[02..20] = 110) that keeps the watchdog timer inactive at startup. Startup delay ends when WDI sees its first level transition. The default watchdog timeout period is 10 s.
The configuration can be changed by optional external circuitry implemented on the carrier board.
