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Changes
→SODIMM EVEN pins declaration
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|J1.201||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||||||||
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|J1.203
|DGND
|DGND
|n.a.
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|J1.42||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||C8<br>1||||||||This signal is pulled down by 2.2kOhm resistor<br>See also [[BORA_Lite_SOM/BORA_Lite_Hardware/Peripherals/Watchdog|this page]]
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|J1.44
|SPI0_CS0n
|CPU.PS_MIO1_500
|A7
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|J1.46||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8|||||||| This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
