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==Introduction==
Even if though PL can share main SDRAM with PS, several applications need a dedicated bank for FPGA IPs in order to have exclusive access and to maximize bandwidth. In any case, since this additional SDRAM bank is accessible via AXI bus, it is mapped in the processor's memory space and thus it can be accessed by PS as well.
BoraEVB can optionally be populated with a 16-bit 512MB SDRAM chip that is directly connected to PL (1). This application note describes how to enable the support for this additional memory bank. An example Vivado design is released along with this application note, based on [[Bora_Embedded_Linux_Kit_%28BELK%29#BELK_software_components|BELK 2.1.0]].
