1,606 bytes added,
13:37, 7 September 2023 <section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |2023/09/07
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First Release
|-
|}
<section end="History" />
__FORCETOC__
<section begin="Body" />
== Unboxing ==
The hardware components is shown in the picture below:
[[File:ETRA-EVK.png|thumb| 500px|center | ETRA SBC]]
The default ETRA SBC order code is '''SDCSB70000D1R-00''' and it is composed by:
{| class="wikitable"
! latexfontsize="scriptsize" | Component
! latexfontsize="scriptsize" | Description
|-
| [[File:ETRA-EVK.png|60px|center]]
| ETRA SBC
* SoC: STM STM32MP157AAB3 (STM31MP1 Dual Core - 650MHz - Tj=-40/125°C)
* SDRAM: 512MB
* eMMC: 8GB
|-
| Add-ons
| [[DWS_ADD-ON | DWS]]
|-
| Temperature grade
| Extended SoHo
|-
|}
----
[[Category:ETRA SBC]]