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The following paragraphs describe in detail the available PL I/O pins and how they are routed to the BORA Lite connector. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora Lite design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.
For more details about PCB design considerations, please refer to the [[Integration_guide_(BoraLite)BORA_Lite_SOM/BORA_Lite_Evaluation_Kit/Carrier_board_design/Integration_Guide#Advanced_routing_and_carrier_board_design_guidelines | Advanced routing and carrier board design guidelines]] article.
The following table reports the I/O banks characteristics:
