Bureaucrats, dave_user, Administrators
8,157
edits
Changes
→SODIMM EVEN pins declaration
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|J1.14||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||||||Open-drain with internal pull-up (10K) to 3.3VIN
For further details, please refer to [[Power (Bora/BoraLite)|Power Supply]]
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|J1.16||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||n.a.||||||||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply]]
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|J1.18||SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||||||For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
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|J1.20||MRSTN||MTR.MR||6||||||||Optionally internally connected to PORSTn (CPU.PS_POR_B_500)
For further details, please refer to [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
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|J1.22||VBAT_BKP||RTC.VBAT||6||||||||
