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Configuring UART3-4-5 (Naon)

1,573 bytes added, 16:01, 30 January 2013
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=== Introduction ===
DM814x provides up to six UART peripheral interfaces, depending on the selected pin multiplexing. Other than pin multiplexing, UARTs features a clock multiplexing: UARTs 0/1/2 have SYSCLK10 as reference clock, while UARTs 3/4/5 can be configured to have SYSCLK6, SYSCLK8 or SYSCLK10. This article describes how to configure UART3change the reference clock of UARTs 3/4/5. = Default configuration = With the default configuration, UARTs 3/4/5 are driven by the SYSCLK8 clock, which runs at 192 MHz; UARTs 0/1/2 are driven by SYSCLK10, which runs at 48 MHz. In this situation, setting the port speed (using the '''stty''' command, for example) gives the following results: * stty -F /dev/ttyOx speed Y --> port 0/1/2 is configured to run @ X baud* stty -F /dev/ttyOx speed X --> port 3/4/5 is configured to run @ 4*X baud This configuration for ports 3/4/5 can be useful when a high-speed UART is required; in other cases, a standard behavior is preferred for ports 3/4/5. = Change UARTs 3/4/5 reference clock = Register McBSP_UART_CLKSRC (see the DM814x Technical Reference Manual, http://www.ti.com/litv/pdf/sprugz8c - section 2.10, page 672) of the Power, Reset, UART4 and UART5 Clock Management (PRCM) Module allows for selection of the reference clock. This register can be set on Linux adding the following initialization (function <code>init_uart5_clk(void)</code> code to work with standard settingsthe <code>arch/arm/mach-omap2/board-naon.c</code> file: <pre>static void __init init_uart5_clk(void){ __raw_writel((1 << 7), TI814X_PLL_CMGC_MCBSP_UART_CLKSRC); /* sysclk10 as a reference clock */} static void __init naon_init(void){ init_uart5_clk(); omap_serial_init(); .... ....</pre>

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