Open main menu

DAVE Developer's Wiki β

Changes

Hardware reset using MIO pins
The default configuration for the two PHY reset signals is managed - by default - in the BORA and BORA Xpress SOMS using the two dedicated [[BORA_SOM/BORA_Hardware/Peripherals/Processing_System_(PS)| MIO pins]].
Those These MIO pins are connected to the PHY reset signals and the reset pulse is can be generated at using a proper software levelsroutine.
=== U-Boot PHY reset ===
=== kernel PHY reset ===
The Linux kernel is assumed to find the two physical transceivers '''already reset'''. So, the hardware reset is not implemented at ''driver nor userspace'' levels.
==== ethernet ====
8,253
edits