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→SOM J1 ODD pins (1 to 139) declaration
<section begin="History" />
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!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|{{oldid|15431|1.0.0}}|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Nov 2021|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|1.0.1|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Mar 2022|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Updated MIO pins
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<section end="History" />
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| J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500<br>NOR flash<br>NAND flash||CPU.E19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[2]=0)
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| J1.123||SPI0_DQ1/MODE1/NAND_WENAND_WE_B||CPU.PS_MIO3_500<br>NOR flash<br>NAND flash||CPU.F17||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[1]=0)
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| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500<br>NOR flash<br>NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (BOOT_MODE[3]=0)
| J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND flash||CPU.C18||Bank 500||I/O||3.3V||
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| J1.136||NAND_RD_BNAND_RE_B/VCFG1||CPU.PS_MIO8_500<br>NAND flash||CPU.E18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-up (VMODE[1]=1)
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| J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND flash||CPU.D18||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.<br><br>Default configuration: pull-down (VMODE[0]=0)
