Bureaucrats, dave_user, Administrators
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Changes
→SOM J2 EVEN pins (2 to 140) declaration
| J2.88||DGND||DGND||-||-||G||-||Digital ground
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| J2.90||FPGA_INIT_B||FPGA.INIT_B_0||T8||BANK 0||I/O||3.3V||For further details, please refer to [[PL_initialization_signals_(BoraBORA_Xpress_SOM/BoraXBORA_Xpress_Hardware/BoraLite) Power_and_Reset/PL_initialization_signals | PL initialization signals]]
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| J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||V10||BANK 0||I||3.3V||For further details, please refer to [[PL_initialization_signals_(BoraBORA_Xpress_SOM/BoraXBORA_Xpress_Hardware/BoraLite) Power_and_Reset/PL_initialization_signals | PL initialization signals]]
(10 kΩ pull-up resistor is already mounted on BORAX module)
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| J2.94||FPGA_DONE||FPGA.DONE0||T10||BANK 0||I/O||3.3V||For further details, please refer to [[PL_initialization_signals_(BoraBORA_Xpress_SOM/BoraXBORA_Xpress_Hardware/BoraLite) Power_and_Reset/PL_initialization_signals | PL initialization signals]]
|-
| J2.96||WD_SET2||WDT.SET2||6||3.3V||I||3.3V||
| J2.102||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||D10<br>22||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(BoraXpress)Resetscheme#PS_MIO50_501]]
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| J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||C13<br>42||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(BoraXpress)Reset scheme#PS_MIO51_501]]
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| J2.108||SOM_PGOOD||SOM_PGOOD_LOGIC.OUT||n.a.||3.3V||O||3.3V||Internally connected to DGND via 100K resistor
| J2.112||SYS_RSTn||CPU.PS_SRST_B_501 ||C14||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor
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| J2.114||PORSTn||CPU.PS_POR_B_500<br>WD.~WDO<br>NOR.~RESET/RFU||B18<br>7<br>A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistor.<br>For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#PORSTn_.28J2.114.29 | Reset_scheme_(BoraXpress)Reset_scheme#PORSTn]]
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| J2.116||MRSTn||Voltage monitor||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistor
For further details, please refer to [[Reset_scheme_(BORAXpress) BORA_Xpress_SOM/BORA_Xpress_Hardware/Power_and_Reset/Reset_scheme_and_control_signals | Reset_scheme_(BoraXpress)Reset scheme]]
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| J2.118||DGND||DGND||-||-||G||-||Digital ground
