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Pinout (BORAXpress)

1,115 bytes added, 10:44, 22 November 2021
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<section begin=Body/>=Introduction=Connectors and Pinout Table==
This chapter contains the pinout description of the BORA Xpress module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin BORA Xpress connectors.
=== Connectors description ===
In the following table are described the interface connectors on [[:Category:Bora | Bora]] SOM:
{| class="wikitable"
|-
!Connector name
!Connector Type
!Notes
!Carrier board counterpart
|-
|J1, J2, J3
|Hirose FX8C-140S-SV<br>3x140 pins 0.6mm pitch connectors
|
|Hirose FX8C-140P-SV''<x>''
where ''<x''> stays for:
* ''empty'' = 5 mm board-to-board height
* 1 = 6 mm board-to-board height
* 2 = 7 mm board-to-board height
* 4 = 9 mm board-to-board height
* 6 = 11 mm board-to-board height
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:
 
[[File:BORA_Xpress_BOTTOM.png|700px|thumb|BORA Xpress BOTTOM view - J1, J2, J3 connectors (pins 1-139, 2-140)|none]]
 
===Pinout table naming conventions ===
 
Each row in the pinout tables contains the following information:
* {| class="wikitable" style="width:50%;"|-|'''Pin: '''|reference to the connector pin* |-|'''Pin Name: pin ''' | Pin (signal) name on the BORA Xpress connectors* |-|'''Internal <br>connections: connections ''' | Connections to the BORA Xpress components*|-* CPU.<x> : pin connected to CPU (processing system) pad named <x>** FPGA.<x>: pin connected to FPGA (programmable logic) pad named <x>** CAN.<x> : pin connected to the CAN transceiver** LAN.<x> : pin connected to the LAN PHY** USB.<x> : pin connected to the USB transceiver** NAND.<x>: pin connected to the flash NAND** NOR.<x>: pin connected to the flash NOR** SV.<x>: pin connected to voltage supervisor** MTR: pin connected to voltage monitors* |-|'''Ball/pin #: ''' | Component ball/pin number connected to signal|-|'''Voltage''' || I/O voltage levels* 1.8V* Supply Group: Power Supply Group3.3V* U.D. = User Defined|-|'''Type: pin ''' |-| Pin type** I = Input** O = Output** D = Differential** Z = High impedance** S = Power supply voltage** G = Ground** A = Analog signal* Voltage: IA/O voltage levelsG = Analog Ground|}
==SOM J1 odd ODD pins (1 to 139)declaration==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
|}
==SOM J1 even EVEN pins (2 to 140)declaration ==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
|}
==SOM J2 odd ODD pins (1 to 139)declaration ==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
|}
==SOM J2 even EVEN pins (2 to 140)declaration==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
|}
==SOM J3 odd ODD pins (1 to 139)declaration==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
|}
==SOM J3 even EVEN pins (2 to 140)declaration==
{| class="wikitable" {| {{table}}
| style="background:#f0f0f0;" align="center" |'''Pin'''
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