Bureaucrats, dave_user, Administrators
8,186
edits
Changes
no edit summary
{{Applies To BoraX}}
{{InfoBoxBottom}}
<section begin=Body/>
== Reset scheme and voltage monitoring ==
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
* a watchdog timer (Maxim MAX6373). For more details please refer to [[Watchdog_(BORAXpress)|Watchdog]] section.
PORSTn is pulled-up to 3.3VIN through a 2.2kOhm resistor.
=== SYS_RSTn (J2.112) ===
=== PS_MIO50_501 (J2.104) ===
By default, this signal is connected to on-board USB PHY reset input. This allows complete software control of PHY reset sequence, even if FPGA is not programmed. In case this signals must be used to implement different functions on carrier board, alternative routing schemes are available on request in order to free this signal. For more details please refer to department sales.
<section end=Body/>
